Digital image processor for a digital camera

• US 7,321,388 B2
• Filed: 06/24/2003
• Issued: 01/22/2008
• Est. Priority Date: 05/29/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Safai, Mohammad A.
• Primary Examiner(s): Vu, Ngoc-Yen
• Assistant Examiner(s): MADDEN, GREGORY VINCENT
• Application Number:
  US10/603,395
• Publication Number:
  US 20040004664A1
• Time in Patent Office: 1,673 Days
• Field of Search: 348/222.1, 348/280, 348/333.1, 348/312, 348/246, 348/272, 348/254, 358/525, 382/300
• US Class Current: 348/222.1
• CPC Class Codes: H04N 2209/046 Colour interpolation to calculate the missing colour values
• CPC Class Codes: H04N 23/617 Upgrading or updating of programs or applications for camera control
• CPC Class Codes: H04N 23/631 Graphical user interfaces [GUI] specially adapted for controlling image capture or setting capture parameters
• CPC Class Codes: H04N 23/843 Demosaicing, e.g. interpolating colour pixel values
• CPC Class Codes: H04N 23/88 for colour balance, e.g. white-balance circuits or colour temperature control
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/134 based on three different wavelength filter elements
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 5/765 Interface circuits between an apparatus for recording and another apparatus
• CPC Class Codes: H04N 5/772 the recording apparatus and the television camera being placed in the same enclosure
• CPC Class Codes: H04N 5/775 between a recording apparatus and a television receiver
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence
• CPC Class Codes: H04N 9/8047 using transform coding

Abstract

A digital image process for a digital camera contains a preprocessor and a postprocessor. The preprocessor can include, for example, a uniformity corrector, a sampling filter, a modulation transformer, and a ditherer. The postprocessor can include a color interpolator, an RGB reconstruction block, a digital compressor, and a color pattern data buffer. The digital image process is programmable to operate one or more of the processing blocks of one or both the preprocessor and the postprocessor for flexible programming that can adapt to the requirements of various digital camera designs or users.

Claims

1. A digital image processor for use in a digital camera having an imaging device arranged to output digital images and a memory for storing digital images, the digital image processor comprising:

a preprocessor comprising hardware for preprocessing digital images received from the imaging device and storing the digital images in the memory;

a postprocessor comprising hardware arranged to receive digital images and to postprocess the digital images into a viewable form;

a system bus within the digital image processor, wherein the preprocessor, the postprocessor, and an interface for the memory are coupled to the system bus;

wherein the preprocessor includes a non-uniformity corrector capable of correcting non-uniformities included in the digital image received from the imaging device; and

wherein the preprocessor further includes;

a programmable sampling filter that is connected to the non-uniformity corrector and capable of systematically selecting portions of the corrected digital image received from the non-uniformity corrector;

a modular transformer that is connected to the programmable sampling filter and capable of at least correcting aberrations in the sampled digital image received from the programmable sampling filter; and

a ditherer that is connected to the modular transformer and capable of at least correcting aliasing in the digital image received from the modular transformer.

2. A digital image processor as recited in claim 1, wherein the postprocessor includes a color interpolator arranged to derive an unknown pixel color value associated with a first pixel based upon at least one known pixel color value associated with at least one other pixel using pixel color weight factors associated with an image sensor in the imaging device.

3. A digital image processor as recited in claim 2, further including a color pattern setting buffer that is connected to the color interpolator and capable of storing image sensor data associated with the image sensor included in the imaging device, the image sensor data being used to derive the associated pixel color weight factors.

4. A digital image processor as recited in claim 2, wherein the postprocessor further includes an RGB reconstructor that is connected to the color interpolator and capable of converting the digital image to an RGB format as needed.

5. A digital image processor as recited in claim 4, wherein the postprocessor further includes a digital image compressor connected to the color interpolator and the RGB reconstructor, the digital image compressor being capable of compressing digital images.

6. A digital image processor as recited in claim 5, wherein the color interpolator, the RGB reconstructor, and the compressor are each connected to the system bus.

7. A digital image processor as recited in claim 1, wherein the digital image processor further includes an authenticity stamping unit connected to the non-uniformity corrector and the system bus.

8. A digital image processor as recited in claim 7, wherein the authenticity stamping unit includes an authenticity stamper connected to a secure key buffer for storing a secure key, the authenticity stamper being capable of encryptically combining digital camera identification and the secure key with an associated non-uniformity corrected digital image.

9. A digital image processor as recited in claim 8, further comprising:

a memory interface controller connected to the system bus, the memory interface controller being capable of providing control signals suitable for controlling the storing of image data in and the retrieving of image data from the memory;

a central processing unit (CPU) interface operatively connected to the system bus for managing communications between the digital image processor and a digital camera system CPU; and

system clock connected to the system bus, the system clock being capable of providing clock signals.

10. A digital image processor as recited in claim 9, wherein the non-uniformity corrector outputs an associated corrected digital image to the system bus, the digital image, in turn, being capable of storage in the memory in a capture mode.

11. A digital image processor as recited in claim 10, wherein the digital camera further includes an input/output (I/O) block suitable for coupling the microprocessor to external devices.

12. A digital image processor as recited in claim 1, wherein the postprocessor is arranged such that its operation does not interfere with the operation of the preprocessor or taking pictures using the digital camera.

13. A digital image processor as recited in claim 1, wherein:

the digital image processor is operable in a first mode in which data corresponding to preprocessed images from the preprocessor are directed to the memory, thereby bypassing the postprocessor; and

the digital image processor is operable in a second mode in which data corresponding to the preprocessed images from the preprocessor are directed to the postprocessor for postprocessing.

14. A digital camera comprising:

an imaging device arranged to output digital images;

a digital image processor as recited in claim 1; and

memory for storing the digital images.