Arrangement for energy conditioning

• US 7,321,485 B2
• Filed: 12/08/2005
• Issued: 01/22/2008
• Est. Priority Date: 04/08/1997
• Status: Expired due to Fees

• Current Assignee: X2Y Attenuators, LLC
• Original Assignee: X2Y Attenuators, LLC
• Inventors: Anthony, Anthony A., Anthony, William M.
• Primary Examiner(s): Jackson; Stephen W.
• Application Number:
  US11/296,391
• Publication Number:
  US 20060139837A1
• Time in Patent Office: 775 Days
• Field of Search: 361/118
• US Class Current: 361/118
• CPC Class Codes: H01G 4/40 Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03H 2001/0014 Capacitor filters, i.e. capacitors whose parasitic inductance is of relevance to consider it as filter
• CPC Class Codes: H03H 2001/0085 : Multilayer, e.g. LTCC, HTCC, green sheets inside PCB filters H05K
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing

Abstract

Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Claims

1. A method of making a device comprising:

providing at least four pluralities of pathways;

wherein only respective pathways of each one plurality of said at least four pluralities of pathways are electrically coupled to one another;

wherein at least two pluralities of said at least four pluralities of pathways provide shielding for at least two other pluralities of said at least four pluralities of pathways; and

wherein said at least two pluralities that provide shielding include at least one pathway that includes a region that is relatively wide and substantially flat.

2. A method of making a circuit arrangement comprising:

providing at least a first and a second plurality of shielding pathways;

providing at least a first and a second plurality of shielded pathways; and

wherein the shielding pathways and the shielded pathways are alternately arranged within said circuit arrangement;

wherein pathways of the same one of the aforementioned pluralities are electrically coupled to one another;

wherein each of the aforementioned pluralities are electrically isolated from one another; and

wherein said second plurality of shielding pathways includes at least one shielding pathway that includes a region that is relatively wide and substantially flat.

3. A method of making a device comprising:

providing a first electrically conductive shield layer that resides in a first plane;

providing a third electrically conductive shield layer that resides in a third plane;

providing a fifth electrically conductive shield layer that resides in a fifth plane;

wherein said third plane is between said first plane and said fifth plane;

providing a first electrically conductive electrode layer that resides in a second plane, and said second plane is between said first plane and said third plane;

providing a third electrically conductive electrode layer that resides in a fourth plane, said fourth plane is between said third plane and said fifth plane;

wherein said device electrically connects said first electrically conductive shield layer, said third electrically conductive shield layer, and said fifth electrically conductive shield layer to one another;

wherein said first electrically conductive shield layer, said third electrically conductive shield layer, and said fifth electrically conductive shield layer are stacked, said first electrically conductive electrode layer is substantially between said first electrically conductive shield layer and said third electrically conductive shield layer, and said third electrically conductive electrode layer is substantially between said third electrically conductive shield layer and said fifth electrically conductive shield layer;

providing a second electrically conductive shield layer;

providing a fourth electrically conductive shield layer;

providing a sixth electrically conductive shield layer;

providing a second electrically conductive electrode layer;

providing a fourth electrically conductive electrode layer;

wherein said device electrically connects said second electrically conductive shield layer, said fourth electrically conductive shield layer, and said sixth electrically conductive shield layer to one another; and

wherein said second electrically conductive shield layer, said fourth electrically conductive shield layer, and said sixth electrically conductive shield layer are stacked, said second electrically conductive electrode layer is substantially between said second electrically conductive shield layer said fourth electrically conductive shield layer, and said fourth electrically conductive electrode layer is substantially between said fourth electrically conductive shield layer and said sixth electrically conductive shield layer.

4. The device of claim 3 wherein:

said first electrically conductive shield layer and said second electrically conductive shield layer reside in a first plane;

said first electrically conductive electrode layer and said second electrically conductive electrode layer reside in a second plane, and said second plane is between said first plane and said third plane;

said third electrically conductive shield layer and said fourth electrically conductive shield layer reside in a third plane;

said fifth electrically conductive shield layer and said sixth electrically conductive shield layer reside in a fifth plane; and

said third electrically conductive electrode layer and said fourth electrically conductive electrode layer reside in a fourth plane, and said fourth plane is between said third plane and said fifth plane.

5. The method of claim 3 wherein:

said first electrically conductive shield layer, said third electrically conductive shield layer and said fifth electrically conductive shield layer are stacked upon said second electrically conductive shield layer, said fourth electrically conductive shield layer, and said sixth electrically conductive shield layer.

6. The method of claim 5 wherein:

said first electrically conductive electrode layer includes a first electrically conductive electrode layer body region and a first electrically conductive electrode layer tab region, and said first electrically conductive electrode layer tab region protrudes from said first electrically conductive electrode layer body region in a first direction in said second plane; and

said third electrically conductive electrode layer defines a third electrically conductive electrode layer body region and third electrically conductive electrode layer tab region, and said third electrically conductive electrode layer tab region protrudes from said third electrically conductive electrode layer body region in a second direction opposite said first direction.

7. The method of claim 6 wherein:

said second electrically conductive electrode layer includes a second electrically conductive electrode layer body region and a second electrically conductive electrode layer tab region, and said second electrically conductive electrode layer tab region protrudes from said second electrically conductive electrode layer body region in third direction that is perpendicular to said first direction and said second direction; and

said fourth electrically conductive electrode layer defines a fourth electrically conductive electrode layer body region and fourth electrically conductive electrode layer tab region, and said fourth electrically conductive electrode layer tab region protrudes from said fourth electrically conductive electrode layer body region in a fourth direction opposite said third direction.

8. The method of claim 3 further comprising additional electrically conductive electrode layers and additional electrically conductive shield layers.

9. The method of claim 4 further comprising an electrically conductive interconnections between two layers of said device.

10. The method of claim 3 further comprising a sixth electrically conductive shield layer adjacent said first electrically conductive shield layer, and a seventh electrically conductive shield layer adjacent said fifth electrically conductive shield layer.

11. The method of claim 3 further comprising:

a set of electrically conductive interconnections;

a set of pads protruding from a surface of said device, and

wherein each one of said set of electrically conductive interconnections connects to a different one of said set of pads.

12. The method of claim 11 wherein at least some of said set of pads are designed for connection to an integrated circuit.