Compensating for coupling in non-volatile storage

• US 7,321,509 B2
• Filed: 02/16/2007
• Issued: 01/22/2008
• Est. Priority Date: 04/05/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Hemink, Gertjan, Cernea, Raul-Adrian, Chen, Jian
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/675,632
• Publication Number:
  US 20070140006A1
• Time in Patent Office: 340 Days
• Field of Search: 365/185.03, 365/185.2
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3422 Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of an adjacent memory cell.

Claims

1. A non-volatile memory system, comprising:

a first set of non-volatile storage elements capable of storing data for at least a first grouping and a second grouping;

a second set of non-volatile storage elements adjacent to said first set of non-volatile storage elements, said second set of non-volatile storage elements associated with at least four data states; and

one or more managing circuits in communication with said set of non-volatile storage elements, said one or more managing circuits determine charge level data for said second set of non-volatile storage elements, said one or more managing circuits perform multiple read operations using different reference levels distinguishing between two adjacent data states, each of said first set of non-volatile storage elements choose to record information associated with one of said read operations based on charge level data for a respective adjacent non-volatile storage element of said second set of multi-state non-volatile storage elements, said recorded information indicates data values for said first grouping.

2. A non-volatile memory system according to claim 1, wherein:

said different reference levels correspond to a base reference level and set of offsets from said base reference level;

said four data states include a first state, a second state, a third state and a fourth state;

said first state corresponds to erased storage elements; and

said two adjacent data states correspond to said second state and said third state.

3. A non-volatile memory system according to claim 1, wherein:

said one or more managing circuits include a state machine, decoders and sense circuits;

said set of non-volatile storage elements are part of an array of non-volatile storage elements, said array of non-volatile storage elements include word lines and bit lines;

said set of non-volatile storage elements are connected to a first word line; and

said non-volatile storage elements adjacent to said set of non-volatile storage elements are connected to a second word line adjacent to said first word line.

4. A non-volatile memory system according to claim 1, wherein:

said first set of non-volatile storage elements are flash memory devices.

5. A non-volatile memory system according to claim 1, wherein:

said first set of non-volatile storage elements are NAND flash memory devices.

6. A non-volatile memory system according to claim 1, wherein:

said first set of non-volatile storage elements include floating gates.

7. A non-volatile memory system according to claim 1, wherein:

said first set of non-volatile storage elements each include a dielectric region for storing charge.

8. A non-volatile memory system, comprising:

a first set of multi-stage non-volatile storage elements capable of storing data for at least a first page and a second page;

a second set of non-volatile storage elements adjacent to said first set of multi-state non-volatile storage elements, said second set of non-volatile storage elements associated with at least four data states; and

one or more managing circuits in communication with said set of non-volatile storage elements, said one or more managing circuits determine charge level data for said second set of non-volatile storage elements, said one or more managing circuits read first data from said first set of non-volatile storage elements using a reference associated with a first set of two adjacent data states and read second data from said first set of non-volatile storage elements using multiple references associated with a second set of two adjacent data states, each of said first set of non-volatile storage elements choose information associated with one of said multiple references based on charge level data for a respective adjacent non-volatile storage element of said second set of multi-state non-volatile storage elements, said first data and said second data in combination indicate data values for said first page of data.

9. A non-volatile memory system according to claim 8, wherein:

said multiple references correspond to a base reference level and a set of offsets from said base reference level;

said four data states include a first state, a second state, a third state and a fourth state;

said first state corresponds to erased storage elements;

said first set of two adjacent data states includes said first state and said second state;

said reference associated with a first set of two adjacent data states is a voltage level between voltage levels for said first state and voltage levels for said second state;

said second set of two adjacent data states includes said third state and said fourth state; and

said base reference level is a voltage level between voltage levels for said third state and voltage levels for said fourth state.

10. A non-volatile memory system according to claim 8, wherein:

said first set of non-volatile storage elements are flash memory devices; and

said one or more managing circuits include a state machine, decoders and sense amplifiers.

11. A non-volatile memory system according to claim 8, wherein:

said first set of non-volatile storage elements are NAND flash memory devices.

12. A non-volatile memory system, comprising:

a first set of multi-stage non-volatile storage elements capable of storing data for at least a first grouping and a second grouping;

a second set of non-volatile storage elements adjacent to said first set of multi-state non-volatile storage elements, said second set of non-volatile storage elements associated with at least four data states; and

one or more managing circuits in communication with said set of non-volatile storage elements, said one or more managing circuits determine charge level data for said second set of non-volatile storage elements and perform multiple read processes relative to a first reference value for distinguishing threshold voltages relative to two adjacent data states for said first set of non-volatile storage elements, each read process uses a different one of a predetermined set of offsets with said first reference value, each of at least a subset of said first set of non-volatile storage element provides final data from an appropriate one of said read processes corresponding to one offset that is associated with a respective adjacent non-volatile storage element, said one or more managing circuits determine data values for said first grouping based on said final data without using other data from user data read processes based on non-zero offsets to reference values between other pairs of adjacent data states.

13. A non-volatile memory system according to claim 12, wherein:

said one or more managing circuits include a state machine, a decoder and sense circuits;

said first set of non-volatile storage elements are part of an array of non-volatile storage elements, said array of non-volatile storage elements include word lines and bit lines;

said first set of non-volatile storage elements are connected to a first word line; and

said second set of non-volatile storage elements are connected to a second word line adjacent to said first word line.

14. A non-volatile memory system according to claim 12, wherein:

said first set of non-volatile storage elements are flash memory devices.

15. A non-volatile memory system according to claim 12, wherein:

said first set of non-volatile storage elements are NAND flash memory devices.

16. A non-volatile memory system according to claim 12, wherein:

said final data indicates data values for said first grouping of data.

17. A non-volatile memory system according to claim 12, wherein:

said first set of multi-state non-volatile storage elements store data in four data states including a first state, a second state, a third state and a fourth state;

said two adjacent data states are said second state and said third state;

said first reference value corresponds to a voltage level between voltage levels for said second state and voltage levels for said third state; and

said final data indicates data values for said first grouping of data.

18. A non-volatile memory system according to claim 12, wherein:

said one or more managing circuits perform an additional read process relative to a second reference value for distinguishing threshold voltages relative to a different pair of adjacent data states, said additional read process does not include said offsets, each of said first set of non-volatile storage elements provides additional data from said additional read process, said final data and said additional data in combination indicate said data values for said first page of data.

19. A non-volatile memory system according to claim 18, wherein:

said first set of multi-state non-volatile storage elements store data in four data states including a first state, a second state, a third state and a fourth state;

said two adjacent data states are said third state and said fourth state;

said different pair of adjacent data states includes said first state and said second state;

said first reference value corresponds to a voltage level between voltage levels for said third state and voltage levels for said fourth state; and

said second reference value corresponds to a voltage level between voltage levels for said first state and voltage levels for said second state.