Bit stream conditioning circuit having adjustable PLL bandwidth

• US 7,321,612 B2
• Filed: 04/17/2003
• Issued: 01/22/2008
• Est. Priority Date: 07/22/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ghiasi, Ali, Tonietto, Davide
• Primary Examiner(s): Payne; David C.
• Assistant Examiner(s): DSOUZA, JOSEPH FRANCIS A
• Application Number:
  US10/418,035
• Publication Number:
  US 20040022303A1
• Time in Patent Office: 1,741 Days
• Field of Search: 375/222, 375/285, 375/329, 375/333, 370/393, 370/394, 398/1, 398/9, 398/209, 341/101, 714/820, 709/250, 326/29, 330/124
• US Class Current: 375/219
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10027 adjusting the signal strength during recording or reproduction, e.g. variable gain amplifiers optimum power control for optical discs G11B7/125
• CPC Class Codes: G11B 20/10046 filtering or equalising, e.g. setting the tap weights of an FIR filter
• CPC Class Codes: G11B 20/10222 clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation dedicated sync patterns in the modulation code G11B20/1403
• CPC Class Codes: H04J 3/04 Distributors combined with modulators or demodulators pulse distributors in general H03K5/15; pulse counters H03K21/00 - H03K29/06; for telegraphy H04L5/22, H04L13/00 - H04L23/00, H04L25/45; for telephony H04Q11/04
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 1/205 jitter monitoring
• CPC Class Codes: H04L 2025/03401 PSK
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 25/20 Repeater circuits; Relay circuits

Abstract

A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.

Claims

1. A high-speed serial bit stream interface that communicatively couples a line side media to a communication Application Specific Integrate Circuit (ASIC), the high-speed serial bit stream interface comprising:

a line side interface that communicatively couples to the line side media, that receives a RX signal therefrom, and that transmits a conditioned TX signal thereto;

a board side interface that communicatively couples to the communication ASIC, that receives a TX signal therefrom and that transmits a conditioned RX signal thereto;

a RX signal conditioning circuit communicatively coupled between an RX portion of the line side interface and an RX portion of the board side interface;

a TX signal conditioning circuit communicatively coupled between a TX portion of the line side interface and a TX portion of the board side interface;

wherein the RX signal conditioning circuit and the TX signal conditioning circuit operate on a serviced signal including the RX signal and the TX signal, respectively, and each of the RX signal conditioning circuit and the TX signal conditioning circuit include;

a limiting amplifier that receives the respective serviced signal and that amplifies the respective serviced signal to produce the respective serviced signal in a desired output range; and

a clock and data recovery circuit having an adjustable Phase Locked Loop (PLL) bandwidth that communicatively couples to the output of the limiting amplifier and receives, recovers, and reclocks the respective serviced signal; and

wherein the PLL bandwidth of the clock and data recovery circuit servicing the RX signal and the PLL bandwidth of the clock and data recovery circuit servicing the TX signal are separately controlled based upon respective serviced signal characteristics.

2. The high-speed serial bit stream interface of claim 1, wherein the RX signal and the TX signal each comprise a single high-speed serial bit stream.

3. The high-speed serial bit stream interface of claim 1, wherein:

the clock and data recovery circuit that services the TX signal employs a first PLL bandwidth that is based upon a jitter bandwidth of the TX signal that is coupled by the board side interface;

the clock and data recovery circuit that services the RX signal employs a second PLL bandwidth that is based upon a jitter bandwidth of the RX signal that is coupled by the line side interface; and

the first PLL bandwidth differs from the second PLL bandwidth.

4. The high-speed serial bit stream interface of claim 3, wherein:

the first PLL bandwidth is based upon output characteristics of the communication ASIC; and

the second PLL bandwidth is based upon the output characteristics of a communication device that produces the RX signal to the line side interface.

5. The high-speed serial bit stream interface of claim 4, wherein:

in a first configuration, the line side media is a copper media, and wherein the RX signal has a first specified jitter bandwidth; and

in a second configuration, the line side media is an optical media, and wherein the RX signal has a second jitter bandwidth.

6. The high-speed serial bit stream interface of claim 1, wherein the RX signal conditioning circuit and the TX signal conditioning circuit each further comprise:

an output pre-emphasis circuit communicatively coupled to the output of the clock and data recovery circuit that controllably modifies the spectrum of the respective serviced signal to pre-compensate for spectral characteristics of a signal path upon which the respective serviced signal will be output.

7. The high-speed serial bit stream interface of claim 1, wherein the RX signal conditioning circuit and the TX signal conditioning circuit each further comprise:

an equalizer communicatively coupled to the input of the limiting amplifier that controllably spectrally shapes the respective serviced signal to compensate for spectral characteristics of a signal path from which the respective serviced signal was received.

8. The high-speed serial bit stream interface of claim 1, further comprising a Printed Circuit Board upon which the line side interface, the board side interface, the RX signal conditioning circuit, and the TX signal conditioning circuit are mounted.

9. The high-speed serial bit stream interface of claim 8, wherein the line side interface comprises a copper media connector.

10. The high-speed serial bit stream interface of claim 8, wherein the line side interface comprises a fiber optic media connector.

11. A high-speed serial bit stream conditioning circuit comprising:

an equalizer that receives a high-speed serial bit stream and that spectrally shapes the high-speed serial bit stream to produce an equalized high-speed serial bit stream;

a limiting amplifier operably coupled to the output of the equalizer that receives the equalized high-speed serial bit stream and that amplifies the equalized high-speed serial bit stream; and

a clock and data recovery circuit having an adjustable Phase Locked Loop (PLL) bandwidth that communicatively couples to the output of the limiting amplifier and that receives, recovers, and reclocks the equalized high-speed serial bit stream, wherein a PLL bandwidth of the clock and data recovery circuit is set to correspond to a jitter bandwidth of the high-speed serial bit stream, wherein;

in a first configuration, the clock and data recovery circuit employs a first PLL bandwidth corresponding to a jitter bandwidth of a high-speed serial bit stream received on a line side media; and

in a second configuration, the clock and data recovery circuit employs a second PLL bandwidth corresponding to a jitter bandwidth of a high-speed serial bit stream received via a Printed Circuit Board from an integrated circuit, wherein the second PLL bandwidth is less than the first PLL bandwidth.

12. The high-speed serial bit stream conditioning circuit of claim 11, wherein:

the first PLL bandwidth is approximately five to ten megahertz; and

the second PLL bandwidth is approximately five to ten kilohertz.

13. The high-speed serial bit stream conditioning circuit of claim 11, further comprising an output pre-emphasis circuit communicatively coupled to an output of the clock and data recovery circuit.

14. The high-speed serial bit stream conditioning circuit of claim 11, further comprising a Printed Circuit Board upon which the equalizer, the limiting amplifier, and the clock and data recovery circuit are mounted.

15. The high-speed serial bit stream conditioning circuit of claim 14, further comprising a copper media connector communicatively coupled to an output of the clock and data recovery circuit.

16. The high-speed serial bit stream conditioning circuit of claim 14, further comprising a fiber optic media connector operably coupled to an output of the clock and data recovery circuit.

17. The high-speed serial bit stream conditioning circuit of claim 11, wherein the clock and data recovery circuit comprises:

a PLL having a phase detector, a charge pump, and a voltage controlled oscillator, wherein at least one of a phase detector gain, a charge pump current, and a voltage controlled oscillator gain are controllable to adjust the PLL bandwidth of the PLL; and

a data latch that receives the equalized high-speed serial bit stream and reclocks the equalized high-speed serial bit stream based upon an output of the PLL.

18. A method for recovering a high-speed serial bit stream comprising:

receiving the high-speed serial bit stream;

spectrally shaping the high-speed serial bit stream to produce an equalized high-speed serial bit stream;

amplifying the equalized high-speed serial bit stream; and

recovering the equalized high-speed bit stream to produce an output high-speed serial bit stream, wherein recovering the equalized high-speed serial bit stream is performed using a Phase Locked Loop (PLL) having a controllable PLL bandwidth that is set to correspond to a jitter bandwidth of the high-speed serial bit stream, wherein;

in a first configuration, a first PLL bandwidth is employed that corresponds to a jitter bandwidth of a high-speed serial bit stream received on a line side media; and

in a second configuration, a second PLL bandwidth is employed that corresponds to a jitter bandwidth of a high-speed serial bit stream received via a Printed Circuit Board from an integrated circuit, wherein the second PLL bandwidth is less than the first PLL bandwidth.

19. The method of claim 18, wherein:

the first PLL bandwidth is approximately five to ten megahertz; and

the second PLL bandwidth is approximately five to ten kilohertz.