Intralevel decoupling capacitor, method of manufacture and testing circuit of the same

• US 7,323,382 B2
• Filed: 02/16/2007
• Issued: 01/29/2008
• Est. Priority Date: 06/11/1999
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cote, William J., Bracchitta, John A., Pricer, Wilbur D., Ning, Tak H., Bernstein, Kerry
• Primary Examiner(s): Pham; Hoai v
• Application Number:
  US11/707,060
• Publication Number:
  US 20070204447A1
• Time in Patent Office: 347 Days
• Field of Search: 438239-240, 438/253, 438/393, 438/396, 257306-307, 257/310, 257/E21.664
• US Class Current: 438/239
• CPC Class Codes: H01G 4/1272 Semiconductive ceramic capacitors
• CPC Class Codes: H01G 4/35 Feed-through capacitors or anti-noise capacitors
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/435 Solid dielectric type

Abstract

A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Claims

1. A method of manufacturing a capacitor, the method comprising:

depositing high dielectric material on a first low dielectric material;

etching a trough region in said high dielectric material;

filling said trough region with metal; and

depositing second low dielectric material on said trough region filled with said metal and said high dielectric material.

2. The method of claim 1, further comprising:

depositing an etch stop layer on said first low dielectric material such that said etch stop layer is between said high dielectric material and said first low dielectric material.

3. The method of claim 2, further comprising:

removing said etch stop layer from areas within said trough region after etching said trough and prior to filling said trough region with said metal.

4. The method of claim 2, wherein said etch stop layer comprises one of diamond-like carbon and silicon nitride.

5. The method of claim 2, wherein said filling said trough region with metal comprises forming interdigitized metal wires in said trough region.

6. The method of claim 5, further comprising:

planarizing an upper surface of said high dielectric material and an upper surface of said interdigitized metal wires.

7. The method of claim 5, wherein sidewalls of adjacent fingers of said interdigitized metal wires form plates of said capacitor.

8. The method of claim 2, wherein said etching said trough region in said high dielectric material comprises etching said high dielectric material down to said etch stop layer.

9. The method of claim 1, wherein said high dielectric material comprises a dielectric constant that is higher than dielectric constants of said first and second low dielectric materials.

10. The method of claim 1, wherein said etching said trough region comprises:

forming a first trough pattern in said high dielectric material; and

forming a second trough pattern in said high dielectric material such that said second trough pattern is interleaved with said first trough pattern in a direction parallel to a plane of said high dielectric material.

11. The method of claim 10, wherein said first and second trough patterns comprise comb-shaped patterns.

12. The method of claim 1, wherein said high dielectric material comprises tantalum pentoxide.

13. The method of claim 1, wherein said high dielectric material comprises silicon nitride.

14. The method of claim 1, wherein said first low dielectric material comprises one of fluorinated oxide, hydrogen silsesquioxane (HSQ) and silk.