Substrate having silicon germanium material and stressed silicon nitride layer

• US 7,323,391 B2
• Filed: 01/15/2005
• Issued: 01/29/2008
• Est. Priority Date: 01/15/2005
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Arghavani, Reza
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US11/037,684
• Publication Number:
  US 20060160314A1
• Time in Patent Office: 1,109 Days
• Field of Search: 438/199, 438/275, 438/285, 257/E29.105, 257/E29.107, 257/E29.108, 257/E29.104
• US Class Current: 438/285
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of fabricating a semiconductor device includes providing a region having doped silicon region on a substrate, and forming a silicon germanium material adjacent to the region on the substrate. A stressed silicon nitride layer is formed over at least a portion of the doped silicon region on the substrate. The silicon germanium layer and stressed silicon nitride layer induce a stress in the doped silicon region of the substrate. In one version, the semiconductor device has a transistor with source and drain regions having the silicon germanium material, and the doped silicon region forms a channel that is configured to conduct charge between the source and drain regions. The stressed silicon nitride layer is formed over at least a portion of the channel, and can be a tensile or compressively stressed layer according the desired device characteristics.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

(a) forming a doped silicon region on a substrate;

(b) forming on the substrate, a silicon germanium material adjacent to the doped silicon region to induce a stress in the doped silicon region;

(c) forming on the substrate, a stressed silicon nitride layer over at least a portion of the doped silicon region to further stress the doped silicon region; and

(d) forming a stressed dielectric layer having a tensile stress of at least about 200 MPa over at least a portion of the stressed silicon nitride layer.

2. A method according to claim 1 wherein (b) comprises epitaxially growing silicon germanium material on the substrate, the silicon germanium material having the chemical stoichiometry of Si_1-xGe_x, where x is from about 0.15 to about 0.3.

3. A method according to claim 1 wherein (b) comprises forming silicon germanium material having a chemical stoichiometry of Si_1-xGe_x, where x is selected to induce a stress of at least about 1 GPa in the doped silicon region.

4. A method according to claim 1 wherein (a) comprises forming a transistor having a source and drain, a channel between the source and drain, and a gate above the channel, and (b) comprises forming the silicon germanium material to extend throughout the source and drain.

5. A method according to claim 1 wherein (c) comprises forming a stressed silicon nitride layer comprising a compressive stress having an absolute value of at least about 2.5 GPa.

6. A method according to claim 1 wherein (c) comprises forming a stressed silicon nitride layer comprising a tensile stress of at least about 1.5 GPa.

7. A method according to claim 6 further comprising forming a stressed silicon oxide layer surrounding at least part of the source and drain, the stressed silicon oxide layer having a tensile stress of at least about 800 MPa.

8. A method according to claim 1 further comprising forming a stressed metal silicide layer over at least a portion of the silicon germanium material.

9. A semiconductor device fabricated according to the method of claim 1.

27. A method according to claim 1 wherein the stressed dielectric layer comprises one of borophosphosilicate, phosphosilicate, borosilicate, and phosphosilicate glass.

10. A method of fabricating a semiconductor device, the method comprising:

(a) forming a transistor on a substrate by;

(i) forming a source and a drain on the substrate, each of the source and drain comprising silicon germanium material extending throughout the source and drain; and

(ii) forming a channel region configured to conduct charge between the source and drain, the channel region comprising doped silicon, whereby stress is induced in the channel region by the silicon germanium material extending throughout the source and drain; and

(b) forming a stressed silicon nitride layer over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region; and

(c) forming a stressed dielectric layer over at least a portion of the stressed silicon nitride layer,

whereby the silicon germanium material, overlying stressed silicon nitride layer and stressed dielectric layer induce stress in the channel region that increases the carrier mobility of channel region.

11. A method according to claim 10 wherein (a) comprises epitaxially growing the silicon germanium in the source and drain, the silicon germanium material having the chemical stoichiometry of Si_1-xGe_x, where x is from about 0.15 to about 0.3.

12. A method according to claim 10 wherein (a) comprises forming source and drain comprising silicon germanium material having a chemical stoichiometry of Si_1-xGe_x, where x is selected to induce a stress of at least about 1 Pa in the channel region.

13. A method according to claim 10 wherein (b) comprises depositing a layer of silicon nitride by a chemical vapor deposition method having deposition parameters selected to deposit a layer of silicon nitride having a compressive stress having an absolute value of at least about 2.5 GPa.

14. A method according to claim 10 wherein (b) comprises depositing a layer of silicon nitride by a chemical vapor deposition method having deposition parameters selected to deposit a layer of silicon nitride having a tensile stress of at least about 1.5 GPa.

15. A method according to claim 10 wherein the stressed dielectric layer has a tensile stress of at least about 200 MPa.

16. A method according to claim 10 further comprising forming a stressed silicon oxide layer surrounding at least part of the drain and source, the stressed silicon oxide layer having a tensile stress of at least about 800 MPa.

17. A method according to claim 10 further comprising forming a stressed metal silicide layer over at least a portion of the source and drain.

18. A semiconductor device comprising:

(a) a transistor comprising;

(i) source and drain comprising silicon germanium material; and

(ii) a channel region configured to conduct charge between the source and drain, the channel region comprising doped silicon, whereby stress is induced in the channel region by the silicon germanium material;

(b) a stressed silicon nitride layer over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region, and

(c) a stressed dielectric layer having a tensile stress of at least about 200 MPa over at least a portion of the stressed silicon nitride layer,

whereby the silicon germanium material, overlying stressed silicon nitride layer and stressed dielectric layer induce stress in the channel region that increases the carrier mobility of the channel region.

19. A device according to claim 18 wherein the source and drain comprise epitaxially grown silicon germanium material, the silicon germanium material having the chemical stoichiometry of Si_1-xGe_x, where x is from about 0.15 to about 0.3.

20. A device according to claim 18 wherein the source and drain comprise silicon germanium material extending throughout the source and drain, the silicon germanium material having a chemical stoichiometry of Si_1-xGe_x, where x is selected to induce a stress of at least about 1 GPa in the channel region.

21. A device according to claim 18 wherein the stressed silicon nitride layer comprises a compressive stress having an absolute value of at least about 2.5 GPa.

22. A device according to claim 18 wherein the stressed silicon nitride layer comprises a tensile stress at least about 1.5 GPa.

23. A device according to claim 22 further comprising a stressed silicon oxide layer surrounding at least part of the drain and source, the stressed silicon oxide layer having a tensile stress of at least about 800 MPa.

24. A device according to claim 18 further comprising a stressed metal silicide layer over at least a portion of the source and drain.

25. A method of fabricating a semiconductor device, the method comprising:

(a) forming a transistor on a substrate by;

(i) forming a source and a drain on the substrate, each of the source and drain comprising silicon germanium material extending throughout the source and drain; and

(ii) forming a channel region configured to conduct charge between the source and drain, the channel region comprising germanium, whereby stress is induced in the channel region by the silicon germanium material in the source and drain; and

(b) forming a stressed silicon nitride layer over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region,

whereby the silicon germanium material and the overlying stressed silicon nitride layer induce stress in the channel region that increases the carrier mobility of the channel region.

26. A semiconductor device comprising:

(a) a transistor comprising;

(i) source and drain comprising silicon germanium material extending throughout the source and drain; and

(ii) a channel region configured to conduct charge between the source and drain, the channel region comprising germanium, whereby stress is induced in the channel region by the silicon germanium material; and

(b) a stressed silicon nitride layer over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region,

whereby the silicon germanium material and the overlying stressed silicon nitride layer induce stress in the channel region that increase the carrier mobility of the channel region.

28. A method of fabricating a semiconductor device, the method comprising:

(a) forming a transistor on a substrate by;

(i) forming a source and a drain on the substrate, each of the source and drain comprising silicon germanium material extending throughout the source and drain, the silicon germanium material having a chemical stoichiometery of Si_1-xGe_x, where x is from about 0.15 to about 0.3; and

(ii) forming a channel region configured to conduct charge between the source and drain, the channel region comprising doped silicon, whereby stress is induced in the channel region by the silicon germanium material in the source and drain; and

(b) forming a stressed silicon nitride layer having a tensile stress of at least about 1.5 GPa over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region; and

(c) forming a stressed dielectric layer having a tensile stress of at least about 200 MPa over at least a portion of the stressed silicon nitride layer,

whereby the silicon germanium material, overlying stressed silicon nitride layer and stressed dielectric layer induce stress in the channel region that increases the carrier mobility of channel region.

29. A semiconductor device comprising:

(a) a transistor comprising;

(i) a source and drain comprising silicon germanium material extending throughout the source and drain, the silicon germanium material having a chemical stoichiometery of Si_1-xGe_x, where x is from about 0.15 to about 0.3; and

(ii) a channel region configured to conduct charge between the source and drain, the channel region comprising germanium, whereby stress is induced in the channel region by the silicon germanium material;

(b) a trench adjacent to the transistor and comprising a stressed dielectric material, the trench having a width and height, the width greater than the height;

(c) a stressed silicon nitride layer with a compressive stress having an absolute value of at least about 2.5 GPa over at least a portion of the transistor, the stressed silicon nitride layer being capable of inducing stress in the channel region; and

(d) a stressed dielectric layer over at least a portion of the stressed silicon nitride layer,

whereby the silicon germanium material and the overlying stressed silicon nitride layer induce stress in the channel region that increases the carrier mobility of the channel region.