Electrical interconnection structure formation

• US 7,323,780 B2
• Filed: 11/10/2005
• Issued: 01/29/2008
• Est. Priority Date: 11/10/2005
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Muzzy, Christopher D., Daubenspeck, Timothy H., Sauter, Wolfgang, Gambino, Jeffrey P.
• Primary Examiner(s): Smith; Zandra V.
• Assistant Examiner(s): Thomas; Toniae M
• Application Number:
  US11/164,107
• Publication Number:
  US 20070105359A1
• Time in Patent Office: 810 Days
• Field of Search: 438613-614, 257737-738, 257780-781, 257/E23.021, 257/E23.069, 257/E21.508
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/11902 Multiple masking steps
• CPC Class Codes: H01L 2224/11912 the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN

Abstract

An electrical interconnection structure and method for forming. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.

Claims

1. A method for forming an electrical structure, comprising:

providing a substrate comprising a first electrically conductive pad and a second electrically conductive pad formed within a volumetric portion of the substrate and a first dielectric layer over a surface of said substrate, a surface of said first electrically conductive pad, and a surface of said second electrically conductive pad;

forming a first via and a second via in said first dielectric layer, said first via located over a portion of said surface of said first electrically conductive pad, said second via located over a portion of said surface of said second electrically conductive pad;

forming a metallic layer over a surface of said first dielectric layer and within said first via and said second via;

forming a second dielectric layer over a surface of said metallic layer;

removing a first portion, a second portion, and a third portion of said second dielectric layer, said first portion removed from over and within said first via, said second portion removed from over and within said second via, and said third portion removed from between said first via and said second via;

forming a ball limiting metallization layer within said first via and said second via, over a portion of said surface of said metallic layer, and over a surface of said second dielectric layer that remains after said removing said first portion, said second portion, and said third portion of said second dielectric layer;

forming a photoresist layer over a surface of said ball limiting metallization layer;

forming a first opening in said photoresist layer by removing a first portion of said photoresist layer located within and over said first via and extending laterally over and parallel to a portion of said surface of said ball limiting metallization layer;

forming a second opening in said photoresist layer by removing a second portion of said photoresist layer located within and over said second via and extending laterally over and parallel to a portion of said surface of said ball limiting metallization layer; and

forming a first solder structure within said first opening and a second solder structure within said second opening.

2. The method of claim 1, further comprising:

forming a third opening between said first solder structure and said second solder structure by removing a third portion of said photoresist layer located between said first solder structure and said second solder structure, a portion of said ball limiting metallization layer located between said first solder structure and said second solder structure, and a portion of said metallic layer located between said first solder structure and said second solder structure.

3. The method of claim 1, further comprising:

reflowing said first solder structure to form a first solder ball; and

reflowing said second solder structure to form a second solder ball.

4. The method of claim 3, further comprising cleaning a surface of said first solder ball and a surface of said second solder ball.

5. The method of claim 1, wherein said first dielectric layer comprises more than one layer of dielectric material.

6. The method of claim 1, wherein said metallic layer comprises a material selected from the group consisting of tantalum and tantalum nitride.

7. The method of claim 1, wherein said forming metallic layer comprises using a physical vapor deposition process.

8. The method of claim 1, wherein said second dielectric layer comprises a polyamide layer.

9. The method of claim 1, wherein said metallic layer comprises a thickness of at least 250 angstroms.

10. The method of claim 1, wherein said first dielectric layer and said second dielectric layer each comprise a different dielectric material.

11. The method of claim 1, wherein each of said first solder structure and said second solder structure comprises a substantially lead free solder composition.