Method and circuit for measuring capacitance and capacitance mismatch

• US 7,323,879 B2
• Filed: 09/30/2004
• Issued: 01/29/2008
• Est. Priority Date: 09/30/2004
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Kuo, Shu-Hua, Li, Jui-Ting
• Primary Examiner(s): Deb; Anjan
• Assistant Examiner(s): He; Amy
• Application Number:
  US10/711,667
• Publication Number:
  US 20060085714A1
• Time in Patent Office: 1,216 Days
• Field of Search: 324/519, 324/537
• US Class Current: 324/519
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 31/318533 using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Abstract

A circuit and method for measuring capacitance and capacitance mismatch of at least one capacitor pair are provided. The circuit includes a first switch, a second switch, a third switch and a P-type transistor. A terminal of the first switch is connected to a terminal of a first capacitor, and a terminal of the second switch is connected to a terminal of a second capacitor. A terminal of the third switch is connected to another terminal of the first capacitor and another terminal of the second capacitor, and a gate of the P-type transistor is connected to another terminal of the third switch. When the first, second and third switches are turned on, a capacitance of the first capacitor, a capacitance of the second capacitor, or a capacitance mismatch between the first and second capacitances is measured.

Claims

1. A method of measuring at least two capacitor pairs, wherein each of the capacitor pairs comprises at least a first capacitor and a second capacitor, the method comprising:

providing a first switch to each capacitor pair respectively, each first switch having a first terminal and a second terminal, wherein the first terminal of each first switch is connected to a terminal of the first capacitor of the corresponding capacitor pair, and the second terminal of each first switch is connected to a first pad respectively;

providing a second switch to each capacitor pair respectively, each second switch having a first terminal and a second terminal, wherein the first terminal of each second switch is connected to a terminal of the second capacitor of the corresponding capacitor pair, and the second terminal of each second switch is connected to a second pad respectively;

providing a third switch to each capacitor pair respectively, each third switch having a first terminal and a second terminal, wherein the first terminal of each third switch is connected to another terminal of the first capacitor and another terminal of the second capacitor of the corresponding capacitor pair; and

providing a P-type transistor, the P-type transistor having a gate, a drain and source, wherein the gate of the P-type transistor is connected to the second terminal of each third switch the drain of the P-type transistor is connected to a third pad, and the source of the P-type transistor is connected to a fourth pad;

wherein a capacitance of one of the first capacitors, a capacitance of one of the second capacitors, or a ratio of a difference between the capacitance of the one of the first capacitors and the capacitance of the one of the second capacitors to an average of the capacitance of the one of the first capacitors and the capacitance of the one of the second capacitors is measured via the first pad, the second pad, the third pad and the fourth pad.

2. The method of claim 1, wherein when the first switch, the second switch and the third switch of one of the capacitor pairs are turned on, for the one of the capacitor pairs, the capacitance of the first capacitor thereof, the capacitance of the second capacitor thereof or a ratio of a difference between the capacitance of the first capacitor and the capacitance of the second capacitor to an average of the capacitance of the first capacitor and the capacitance of the second capacitor thereof is measured via the first pad, the second pad, the third pad and the fourth pad.

3. The method of claim 1, wherein when the first switch and the third switch of one of the capacitor pairs, and die second switch and the third switch of another one of the capacitor pairs are turned on, the capacitance of the first capacitor of the one of the capacitor pairs, the capacitance of the second capacitor of the another one of the capacitor pairs, or a ratio of a difference between the capacitance of the first capacitor of the one of the capacitor pairs and the capacitance of the second capacitor of the another one of the capacitor pairs to an average of the capacitance of the first capacitor of the one of the capacitor pairs and the capacitance of the second capacitor of the another one of the capacitor pairs is measured via the first pad, the second pad, the third pad and fourth pad.

4. The method of claim 1, further comprising:

providing a selection circuit, connected to all of the first switches, the second switches and the third switches to selectively turn on or turn off the first switches, the second switches or the third switches.

5. The method of claim 4, further comprising a step of automatically operating the method via the selection circuit.

6. The method of claim 4, wherein the selection circuit comprises a shift register.

7. A circuit for measuring at least two capacitor pairs, wherein each of the capacitor pairs comprises at least a first capacitor and a second capacitor, the circuit comprising:

a plurality of first switches, each first switch having a first terminal and a second terminal, wherein the first terminal of each first switch is connected to a terminal of the first capacitor of each of the capacitor pairs, and the second terminal of each first switch is connected to a first pad;

a plurality of second switches, each second switch having a first terminal and a second terminal, wherein the first terminal of each second switch is connected to a terminal of the second capacitor of each of the capacitor pairs, and the second terminal of each second switch is connected to a second pad;

a plurality of third switches, each third switch having a first terminal and a second terminal, wherein the first terminal of each third switch is connected to another terminal of the first capacitor and another terminal of the second capacitor of each of the capacitor pairs; and

a P-type transistor, having a gate, a drain and source, wherein the gate of the P-type transistor is connected to the second terminal of each third switch, the drain of the P-type transistor is connected to a third pad, and the source of the P-type transistor is connected to a fourth pad;

wherein a capacitance of one of the first capacitors, a capacitance of one of the second capacitors, or a ratio of a difference between the capacitance of the one of the first capacitors and the capacitance of the one of the second capacitors to an average of the capacitance of the one of the first capacitors and the capacitance of the one of the second capacitors is measured via the first pad, the second pad, the third pad, and the fourth pad.

8. The circuit of claim 7, wherein when the first switch, the second switch and the third switch of one of the capacitor pairs are turned on, for the one of the capacitor pairs, the capacitance of the first capacitor thereof, the capacitance of the second capacitor thereof, or a ratio of a difference between the capacitance of the first capacitor and the capacitance of the second capacitor to an average of the capacitance of the first capacitor and the capacitance of the second capacitor thereof is measured.

9. The circuit of claim 7, wherein when the first switch and the third switch of one of the capacitor pairs, and the second switch and the third switch of another one of the capacitor pairs are tuned on, the capacitance of the first capacitor of the one of the capacitor pairs, the capacitance of the second capacitor of the another one of the capacitor pairs, or a ratio of a difference between the capacitance of the first capacitor of the one of the capacitor pairs and the capacitance of the second capacitor of the another one of the capacitor pairs to an average of the capacitance of the first capacitor of the one of the capacitor pairs and the capacitance of the second capacitor of the another one of the capacitor pairs is measured via the first pad, the second pad, the third pad and the fourth pad.

10. The circuit of claim 7, further comprising:

a selection circuit, connected to all of the first switches, the second switches and the third switch to selectively turn on or turn off the first switches, the second switches or the third switches.

11. The circuit of claim 10, further comprising a step of automatically operating the circuit via the selection circuit.

12. The circuit of claim 10, the selection circuit comprises a shift register.