Self-calibrating continuous-time delta-sigma modulator
First Claim
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1. A data conversion circuit comprising:
- a delta-sigma modulator for generating a discrete-time output sequence, wherein the delta-sigma modulator comprises a continuous-time loop filter comprising at least two integrator circuits and a switching circuit configured for selectively bypassing at least one of the integrator circuits, the switching circuit bypasses at least one of the integrator circuits during calibration such that the delta-sigma modulator has a lower order continuous-time loop filter and restores at least one of the bypassed integrator circuits after calibration such that the delta-sigma modulator has a higher order continuous-time loop filter, and the delta-sigma modulator is configured to receive a calibration signal and a continuous-time input signal;
an estimator circuit configured to generate an error signal based on the calibration signal and the discrete-time output sequence; and
a controller circuit configured to adjust at least one time constant of the integrator circuits based on the error signal.
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Abstract
A self-calibrating continuous-time delta-sigma modulator determines whether time constants of its internal integrators are too large or too small by injecting a calibrating sequence into the modulator and examining a correlation between the calibrating sequence and a modulator output sequence. Then the time constants of the internal integrators are adjusted accordingly. In one embodiment, the correlation is exploited based on matching a noise transfer function of the modulator using an adaptive filter based on a least mean square (LMS) algorithm.
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Citations
21 Claims
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1. A data conversion circuit comprising:
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a delta-sigma modulator for generating a discrete-time output sequence, wherein the delta-sigma modulator comprises a continuous-time loop filter comprising at least two integrator circuits and a switching circuit configured for selectively bypassing at least one of the integrator circuits, the switching circuit bypasses at least one of the integrator circuits during calibration such that the delta-sigma modulator has a lower order continuous-time loop filter and restores at least one of the bypassed integrator circuits after calibration such that the delta-sigma modulator has a higher order continuous-time loop filter, and the delta-sigma modulator is configured to receive a calibration signal and a continuous-time input signal; an estimator circuit configured to generate an error signal based on the calibration signal and the discrete-time output sequence; and a controller circuit configured to adjust at least one time constant of the integrator circuits based on the error signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of calibrating a delta-sigma modulator that receives a continuous-time input signal, generates a discrete-time output sequence, and comprises at least a first integrator and a second integrator, the method comprising:
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reducing a number of integrators in a processing loop to lower the delta-sigma modulator'"'"'s order during calibration; injecting a calibration signal into the lower order delta-sigma modulator; generating an error signal based on the calibration signal and the discrete-time output sequence; and adjusting a time constant for at least one of the integrators in the processing loop of the lower order delta-sigma modulator in response to the error signal. - View Dependent Claims (15, 16, 17, 18)
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19. A data conversion circuit comprising:
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an adjustable order modulator for receiving a calibration signal and a continuous-time input signal to generate a discrete-time output sequence, wherein the adjustable order modulator comprises a plurality of integrators and a switch module for reducing a number of the integrators in a processing loop of the data conversion circuit during calibration; an estimator circuit for generating an error signal based on the calibration signal and the discrete-time output sequence; and a controller circuit for adjusting a time constant for at least one of the integrators in the data conversion circuit in response to the error signal. - View Dependent Claims (20, 21)
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Specification