Non-volatile memory architecture employing bipolar programmable resistance storage elements
First Claim
1. A nonvolatile memory array, comprising:
- a plurality of word lines;
a plurality of bit lines;
a plurality of source lines; and
a plurality of nonvolatile memory cells, each of at least a subset of the plurality of memory cells having a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines, at least one of the memory cells comprising;
a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a first line of a corresponding bit line/source line pair; and
a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a second line of the corresponding bit line/source line pair, and the gate connecting to a corresponding one of the word lines;
wherein for any subset of at least four memory cells connected to a same bit line, each of the four memory cells being adjacent to one another, at least two adjacent memory cells in the subset share a same word line and at least two adjacent memory cells in the subset share a same source line.
7 Assignments
0 Petitions
Accused Products
Abstract
A nonvolatile memory array includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of nonvolatile memory cells. Each of at least a subset of the plurality of memory cells has a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines. At least one of the memory cells includes a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to one of a corresponding first one of the bit lines and a corresponding first one of the source lines, and a metal-oxide-semiconductor device including first and second source/drains and a gate. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a corresponding second one of the bit lines, and the gate is adapted for connection to a corresponding one of the word lines. For at least a subset of the plurality of memory cells, each pair of adjacent memory cells along a given word line shares either the same bit line or the same source line.
-
Citations
20 Claims
-
1. A nonvolatile memory array, comprising:
-
a plurality of word lines; a plurality of bit lines; a plurality of source lines; and a plurality of nonvolatile memory cells, each of at least a subset of the plurality of memory cells having a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines, at least one of the memory cells comprising; a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a first line of a corresponding bit line/source line pair; and a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a second line of the corresponding bit line/source line pair, and the gate connecting to a corresponding one of the word lines; wherein for any subset of at least four memory cells connected to a same bit line, each of the four memory cells being adjacent to one another, at least two adjacent memory cells in the subset share a same word line and at least two adjacent memory cells in the subset share a same source line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. An integrated circuit including at least one nonvolatile memory array, the at least one memory array comprising:
-
a plurality of word lines; a plurality of bit lines; a plurality of source lines; and a plurality of nonvolatile memory cells, each of at least a subset of the plurality of memory cells having a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines, at least one of the memory cells comprising; a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a first line of a corresponding bit line/source line pair; and a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a second line of the corresponding bit line/source line pair, and the gate connecting to a corresponding one of the word lines; wherein for any subset of at least four memory cells connected to a same bit line, each of the four memory cells being adjacent to one another, at least two adjacent memory cells in the subset share a same word line and at least two adjacent memory cells in the subset share a same source line. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
-
Specification