Non-volatile memory architecture employing bipolar programmable resistance storage elements

• US 7,324,366 B2
• Filed: 04/21/2006
• Issued: 01/29/2008
• Est. Priority Date: 04/21/2006
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Meijer, Gerhard Ingmar, Lam, Chung Hon, Bednorz, Johannes Georg
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/409,440
• Publication Number:
  US 20070247893A1
• Time in Patent Office: 648 Days
• Field of Search: 365/148, 365/100, 365/103, 365/104, 365/177
• US Class Current: 365/148
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A nonvolatile memory array includes a plurality of word lines, a plurality of bit lines, a plurality of source lines, and a plurality of nonvolatile memory cells. Each of at least a subset of the plurality of memory cells has a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines. At least one of the memory cells includes a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to one of a corresponding first one of the bit lines and a corresponding first one of the source lines, and a metal-oxide-semiconductor device including first and second source/drains and a gate. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a corresponding second one of the bit lines, and the gate is adapted for connection to a corresponding one of the word lines. For at least a subset of the plurality of memory cells, each pair of adjacent memory cells along a given word line shares either the same bit line or the same source line.

Claims

1. A nonvolatile memory array, comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of source lines; and

a plurality of nonvolatile memory cells, each of at least a subset of the plurality of memory cells having a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines, at least one of the memory cells comprising;

a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a first line of a corresponding bit line/source line pair; and

a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a second line of the corresponding bit line/source line pair, and the gate connecting to a corresponding one of the word lines;

wherein for any subset of at least four memory cells connected to a same bit line, each of the four memory cells being adjacent to one another, at least two adjacent memory cells in the subset share a same word line and at least two adjacent memory cells in the subset share a same source line.

2. The memory array of claim 1, wherein the bit lines are arranged substantially parallel relative to one another.

3. The memory array of claim 1, wherein the word lines are arranged substantially parallel relative to one another.

4. The memory array of claim 1, wherein the plurality of word lines is arranged substantially orthogonal to the plurality of bit lines and the plurality of source lines.

5. The memory array of claim 1, wherein the bipolar programmable storage element comprises a magnetic tunnel junction device.

6. The memory array of claim 1, wherein the bipolar programmable storage element in at least one of the plurality of nonvolatile memory cells comprises a transition metal oxide.

7. The memory array of claim 6, wherein the transition metal oxide is doped at a prescribed doping concentration with at least one of chromium, manganese, and vanadium.

8. The memory array of claim 1, wherein a logic state of the bipolar programmable storage element in a given one of the plurality of nonvolatile memory cells is written by substantially concurrently applying a logic high voltage potential to a corresponding word line connected to the given memory cell, applying a logic high voltage potential to a first line of a corresponding bit line/source line pair, applying a logic low voltage potential to a second line of the corresponding bit line/source line pair, and applying a substantially same voltage potential to a bit line and a source line in each bit line/source line pair corresponding to other memory cells connected to the corresponding word line, a polarity of the voltage potential across the corresponding bit line/source line pair being indicative of the logic state to be written into the memory cell.

9. The memory array of claim 1, wherein a logic state of the bipolar programmable storage element in a given one of the plurality of nonvolatile memory cells is read by applying a logic high voltage potential to a corresponding word line connected to the given memory cell, and substantially concurrently applying a logic low voltage potential to a first line and applying a read voltage potential to and sensing a current on a second and third line, the first line being a of the corresponding bit line/source line pair, a magnitude of the sensed current being indicative of the logic state of the memory cell.

10. The memory array of claim 1, wherein the memory array is configured to enable two adjacent memory cells connected to a same word line to be read substantially simultaneously.

11. The memory array of claim 10, wherein the two adjacent memory cells are substantially simultaneously read by applying a logic high voltage potential to the word line connected to the adjacent memory cells, and substantially concurrently applying a logic low voltage potential to a first line of each bit line/source line pair corresponding to the adjacent memory cells, the first line being shared by the adjacent memory cells, and applying a read voltage potential to each of a second line of the bit line/source line corresponding to the adjacent memory cells.

12. The memory array of claim 1, wherein the bipolar programmable storage element in at least one of the plurality of nonvolatile memory cells comprises at least one of chromium-doped strontium titanium oxide, strontium titanium oxide, strontium barium titanium oxide, praseodymium calcium manganese oxide, strontium zirconium oxide, and nickel oxide.

13. An integrated circuit including at least one nonvolatile memory array, the at least one memory array comprising:

a plurality of word lines;

a plurality of bit lines;

a plurality of source lines; and

a plurality of nonvolatile memory cells, each of at least a subset of the plurality of memory cells having a first terminal connected to one of the plurality of word lines, a second terminal connected to one of the plurality of bit lines, and a third terminal connected to one of the plurality of source lines, at least one of the memory cells comprising;

a bipolar programmable storage element operative to store a logic state of the memory cell, a first terminal of the bipolar programmable storage element connecting to a first line of a corresponding bit line/source line pair; and

a metal-oxide-semiconductor device including first and second source/drains and a gate, the first source/drain being connected to a second terminal of the bipolar programmable storage element, the second source/drain connecting to a second line of the corresponding bit line/source line pair, and the gate connecting to a corresponding one of the word lines;

wherein for any subset of at least four memory cells connected to a same bit line, each of the four memory cells being adjacent to one another, at least two adjacent memory cells in the subset share a same word line and at least two adjacent memory cells in the subset share a same source line.

14. The integrated circuit of claim 13, wherein a logic state of the bipolar programmable storage element in a given one of the plurality of nonvolatile memory cells is written by substantially concurrently applying a logic high voltage potential to a corresponding word line connected to the given memory cell, applying a logic high voltage potential to a first line of a corresponding bit line/source line pair, applying a logic low voltage potential to a second line of the corresponding bit line/source line pair, and applying a substantially same voltage potential to a bit line and a source line in each bit line/source line pair corresponding to other memory cells connected to the corresponding word line, a polarity of the voltage potential across the corresponding bit line/source line pair being indicative of the logic state to be written into the memory cell.

15. The integrated circuit of claim 13, wherein a logic state of the bipolar programmable storage element in a given one of the plurality of nonvolatile memory cells is read by applying a logic high voltage potential to a corresponding word line connected to the given memory cell, and substantially concurrently applying a logic low voltage potential to a first line and applying a read voltage potential to and sensing a current on a second and third line, the first line being a of the corresponding bit line/source line pair, a magnitude of the sensed current being indicative of the logic state of the memory cell.

16. The integrated circuit of claim 13, wherein the at least one memory array is configured to enable two adjacent memory cells connected to a same word line to be read substantially simultaneously.

17. The integrated circuit of claim 16, wherein the two adjacent memory cells are substantially simultaneously read by applying a logic high voltage potential to the word line connected to the adjacent memory cells, and substantially concurrently applying a logic low voltage potential to a first line of each bit line/source line pair corresponding to the adjacent memory cells, the first line being shared by the adjacent memory cells, and applying a read voltage potential to each of a second line of the bit line/source line corresponding to the adjacent memory cells.

18. The integrated circuit of claim 13, wherein the bipolar programmable storage element in at least one of the plurality of nonvolatile memory cells comprises at least one of chromium-doped strontium titanium oxide, strontium titanium oxide, strontium barium titanium oxide, praseodymium calcium manganese oxide, strontium zirconium oxide, and nickel oxide.

19. The integrated circuit of claim 13, wherein the plurality of word lines is arranged substantially orthogonal to the plurality of bit lines and the plurality of source lines.

20. The integrated circuit of claim 13, wherein the bit lines and source lines are arranged substantially parallel relative to one another.