Method for trimming the temperature coefficient of a floating gate voltage reference

• US 7,324,380 B2
• Filed: 12/15/2006
• Issued: 01/29/2008
• Est. Priority Date: 02/15/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Catalyst Semiconductor Inc (ON Semiconductor Corporation)
• Inventors: Eftimie, Sabin A., Negut, Alina I., Georgescu, Sorin S.
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/611,665
• Publication Number:
  US 20070189069A1
• Time in Patent Office: 410 Days
• Field of Search: 365/185.2, 365/189.11, 365/189.09, 365/189.07, 365/210, 327535-537
• US Class Current: 365/185.2
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a second NVM transistor. During programming, one or more capacitors are connected between the floating gate of the first NVM transistor and ground, and one or more capacitors are connected between the floating gate of the second NVM transistor and ground. The first and second NVM transistors are then coupled to a differential amplifier, which is used to generate a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor. Bipolar transistors are selectively switched between the various capacitors and ground, thereby providing precise adjustment of the temperature coefficient of the voltage reference circuit.

Claims

1. A method of providing a reference voltage in an integrated circuit, comprising:

programming a threshold voltage of a first non-volatile memory (NVM) transistor while coupled with a second NVM transistor;

coupling a first capacitor between a floating gate of the first NVM transistor and a first voltage supply during the programming step;

generating a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor; and

then

adjusting a temperature coefficient associated with the single-ended reference voltage by introducing a first p-n junction in series with the first capacitor.

2. The method of claim 1, wherein the temperature coefficient is reduced by introducing the first p-n junction in series with the first capacitor.

3. The method of claim 1, further comprising:

coupling a second capacitor between the floating gate of the first NVM transistor and the first voltage supply during the programming step; and

adjusting the temperature coefficient associated with the single-ended reference voltage by introducing a second p-n junction in series with the second capacitor.

4. The method of claim 3, wherein the temperature coefficient is adjusted in a first direction by introducing the first and second p-n junctions in series with the first capacitor.

5. The method of claim 1, wherein the first p-n junction is introduced by switching a PNP bipolar transistor into a series connection with the first capacitor.

6. The method of claim 1, wherein the first voltage supply comprises a ground terminal.

7. The method of claim 1, wherein the first p-n junction is introduced between the first capacitor and the first voltage supply.

8. The method of claim 1, wherein the first p-n junction is introduced such that the first p-n junction is forward-biased.

9. The method of claim 1, further comprising:

coupling a second capacitor between a floating gate of the second NVM transistor and the first voltage supply during the programming step; and

adjusting the temperature coefficient associated with the single-ended reference voltage by introducing a second p-n junction in series with the second capacitor.

10. The method of claim 9, wherein the temperature coefficient is adjusted in a first direction by introducing the first p-n junction in series with the first capacitor, and wherein the temperature coefficient is adjusted in a second direction, opposite the first direction, by introducing the second p-n junction in series with the second capacitor.

11. The method of claim 9, wherein the first p-n junction is introduced between the first capacitor and the first voltage supply, and the second p-n junction is introduced between the second capacitor and the first voltage supply.

12. The method of claim 9, wherein the first and second p-n junctions are introduced such that the first and second p-n junctions are forward-biased.

13. The method of claim 1, further comprising selecting a total capacitance coupled between the floating gate of the first NVM transistor and the first voltage supply during the programming step to be equal to a total capacitance coupled between the floating gate of the second NVM transistor and the first voltage supply during the programming step.

14. A method of providing a reference voltage in an integrated circuit, comprising:

programming a threshold voltage of a first non-volatile memory (NVM) transistor while coupled with a second NVM transistor;

coupling a first capacitor between a floating gate of the second NVM transistor and a first voltage supply during the programming step;

generating a single-ended reference voltage in response to the programmed threshold voltage of the first NVM transistor; and

then

adjusting a temperature coefficient associated with the single-ended reference voltage by introducing a first p-n junction in series with the first capacitor.

15. The method of claim 14, wherein the temperature coefficient is increased by introducing the first p-n junction in series with the first capacitor.

16. The method of claim 14, further comprising:

coupling a second capacitor between the floating gate of the second NVM transistor and the first voltage supply during the programming step; and

adjusting the temperature coefficient associated with the single-ended reference voltage by introducing a second p-n junction in series with the second capacitor.

17. The method of claim 14, wherein the first p-n junction is introduced by switching a PNP bipolar transistor into a series connection with the first capacitor.

18. The method of claim 14, wherein the first voltage supply comprises a ground terminal.

19. The method of claim 14, wherein the first p-n junction is introduced between the first capacitor and the first voltage supply.

20. The method of claim 14, wherein the first p-n junction is introduced such that the first p-n junction is forward-biased.

21. The method of claim 14, further comprising selecting a total capacitance coupled between the floating gate of the first NVM transistor and the first voltage supply during the programming step to be equal to a total capacitance coupled between the floating gate of the second NVM transistor and the first voltage supply during the programming step.