Low power high density random access memory flash cells and arrays

• US 7,324,387 B1
• Filed: 04/02/2007
• Issued: 01/29/2008
• Est. Priority Date: 04/18/2006
• Status: Expired due to Fees

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Inventors: Sinai, Keyhan, Prabhakar, Venkatraman, Bergemont, Albert
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/732,323
• Time in Patent Office: 302 Days
• Field of Search: 365/185.33, 365/185.22, 365/185.29, 365/185.18, 365/63, 365/230.03
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

Low power high density random access memory flash cells and arrays using Fowler Nordheim (FN) tunneling for both programming and erasing. The memory array is divided into sectors, each sector comprising a predetermined number of rows. The bit lines are similarly segmented, each global bit line being selectively connectable to a local bit line for each sector, each local bit line being connected to the drains of all floating gate cells in a respective column of each sector. The sources of all floating gate cells in a respective column of each sector are connected to a local source line for that sector, the local source lines for each sector being controllably connectable to respective global source lines. Consequently all floating gate cells within a column of a sector are connected in parallel, source to source and drain to drain. Representative programming and erase voltages not disturbing other cells are disclosed.

Claims

1. A flash memory comprising:

an array of rows and columns of floating gate memory cells, each memory cell having a source, a drain, a gate and a floating gate;

the array including a global bit line and a global source line for each column of cells, the rows of cells being grouped in sectors, each sector including a predetermined number of rows, the drains of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global bit line through first access transistors, the sources of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global source line through second access transistors;

the gates of the floating gate memory cells in each row of floating gate memory cells being connected to a respective word line;

circuitry configured to controllably provide a voltage of a first polarity between the gate and the drain of one or more selected cells in a sector to program the selected cell by Fowler Nordheim tunneling without disturbing the state of other cells; and

,

to controllably provide a voltage of a second polarity opposite the first polarity between the gate and the drain of one or more selected rows of cells to erase the selected rows of cells by Fowler Nordheim tunneling without disturbing cells in unselected rows of cells.

2. The flash memory of claim 1 wherein on erase, the circuitry provides the voltage of a second polarity to a single row in a sector.

3. The flash memory of claim 1 wherein on erase, the circuitry provides the voltage of a second polarity to all rows in a sector.

4. The flash memory of claim 1 wherein adjacent floating gate memory cells within a column of a sector are physically oriented source to source and drain to drain, whereby a single contact may make contact with two drains or two sources.

6. The flash memory of claim 1 wherein the circuitry configured to controllably provide a voltage of a first polarity between the gate and the drain of one or more selected cells in a sector to program the selected cell by Fowler Nordheim tunneling also comprises circuitry for restricting voltages on floating gate memory cells not intended to be programmed to lesser voltages not disturbing the state of the floating gate memory cells not intended to be programmed.

7. The flash memory of claim 1 wherein the circuitry to controllably provide a voltage of a second polarity opposite the first polarity between the gate and the drain of one or more selected rows of cells to erase the selected rows of cells by Fowler Nordheim tunneling without disturbing cells in unselected rows of cells comprises circuitry for restricting voltages on floating gate memory cells not intended to be erased to lesser voltages not disturbing the programming of the floating gate memory cells not intended to be erased.

5. The flash memory of 1 wherein the number of rows in a sector is 64.

8. A flash memory comprising:

an array of rows and columns of floating gate memory cells, each memory cell having a source, a drain, a gate and a floating gate;

the array including a global bit line and a global source line for each column of cells, the rows of cells being grouped in sectors, each sector including a predetermined number of rows, the drains of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global bit line through first access transistors, the sources of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global source line through second access transistors;

the gates of the floating gate memory cells in each row of floating gate memory cells being connected to a respective word line;

circuitry configured to controllably provide a voltage of a first polarity between the gate and the drain of one or more selected cells in a sector to program the selected cell by Fowler Nordheim tunneling and restricting voltages on floating gate memory cells not intended to be programmed to lesser voltages not disturbing the state of the floating gate memory cells not intended to be programmed; and

,

to controllably provide a voltage of a second polarity opposite the first polarity between the gate and the drain of one or more selected rows of cells to erase the selected rows of cells by Fowler Nordheim tunneling and for restricting voltages on floating gate memory cells not intended to be erased to lesser voltages not disturbing the programming of the floating gate memory cells not intended to be erased.

9. The flash memory of claim 8 wherein on erase, the circuitry provides the voltage of a second polarity to a single row in a sector.

10. The flash memory of claim 8 wherein on erase, the circuitry provides the voltage of a second polarity to a all rows in a sector.

11. The flash memory of claim 8 wherein adjacent floating gate memory cells within a column of a sector are physically oriented source to source and drain to drain, whereby a single contact may make contact with two drains or two sources.

12. The flash memory of 8 wherein the number of rows in a sector is 64.

13. A low power program and erase flash memory method comprising:

providing an array of rows and columns of floating gate memory cells, each memory cell having a source, a drain, a gate and a floating gate, the array including a global bit line and a global source line for each column of cells, the rows of cells being grouped in sectors, each sector including a predetermined number of rows, the drains of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global bit line through first access transistors, the sources of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global source line through second access transistors, the gates of the floating gate memory cells in each row of floating gate memory cells being connected to a respective word line;

controllably providing a voltage of a first polarity between the gate and the drain of one or more selected cells in a sector to program the selected cell by Fowler Nordheim tunneling without disturbing the state of other cells; and

,

controllably providing a voltage of a second polarity opposite the first polarity between the gate and the drain of one or more selected rows of cells to erase the selected rows of cells by Fowler Nordheim tunneling without disturbing cells in unselected rows of cells.

14. The method of claim 13 wherein on erase, one row is selected.

15. The method of claim 13 wherein on erase, all rows of a sector are selected.

16. The method of claim 13 wherein adjacent floating gate memory cells within a column of a sector are physically oriented source to source and drain to drain, whereby a single contact may make contact with two drains or two sources.

18. The method of claim 13 wherein controllably providing a voltage of a first polarity between the gate and the drain of one or more selected cells in a sector to program the selected cell by Fowler Nordheim tunneling also restricts voltages on floating gate memory cells not intended to be programmed to lesser voltages not disturbing the state of the floating gate memory cells not intended to be programmed.

19. The flash memory of claim 13 wherein controllably providing a voltage of a second polarity opposite the first polarity between the gate and the drain of one or more selected rows of cells to erase the selected rows of cells by Fowler Nordheim tunneling without disturbing cells in unselected rows of cells also restricts voltages on floating gate memory cells not intended to be erased to lesser voltages not disturbing the programming of the floating gate memory cells not intended to be erased.

17. The method of 13 wherein the number of rows in a sector is 64.

20. A low power program and erase flash memory method comprising:

providing an array of rows and columns of floating gate memory cells, each memory cell having a source, a drain, a gate and a floating gate, the array including a global bit line and a global source line for each column of cells, the rows of cells being grouped in sectors, each sector including a predetermined number of rows, the drains of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global bit line through first access transistors, the sources of all cells in any selected column of any selected sector being coupled together and controllably couplable to a global source line through second access transistors, the gates of the floating gate memory cells in each row of floating gate memory cells being connected to a respective word line;

controllably providing a voltage of a first polarity between the gate and the drain of one or more selected cells in a sector to program the selected cell by Fowler Nordheim tunneling and restricting voltages on floating gate memory cells not intended to be programmed to lesser voltages not disturbing the state of the floating gate memory cells not intended to be programmed; and

,

controllably providing a voltage of a second polarity opposite the first polarity between the gate and the drain of one or more selected rows of cells to erase the selected rows of cells by Fowler Nordheim tunneling and restricting voltages on floating gate memory cells not intended to be erased to lesser voltages not disturbing the programming of the floating gate memory cells not intended to be erased.

21. The method of claim 20 wherein on erase, one row is selected.

22. The method of claim 20 wherein on erase, all rows of a sector are selected.

23. The method of claim 20 wherein adjacent floating gate memory cells within a column of a sector are physically oriented source to source and drain to drain, whereby a single contact may make contact with two drains or two sources.

24. The method of 20 wherein the number of rows in a sector is 64.