Internet protocol (IP) router residing in a processor chipset

• US 7,324,547 B1
• Filed: 12/13/2002
• Issued: 01/29/2008
• Est. Priority Date: 12/13/2002
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Sidenblad, Paul J., Hicok, Gary D., Alfieri, Robert A., Parris, Mark A.
• Primary Examiner(s): To; Doris H.
• Assistant Examiner(s): Moore; Ian N.
• Application Number:
  US10/319,780
• Time in Patent Office: 1,873 Days
• Field of Search: 370/461, 370/413, 370/416, 370/415, 370/414, 370/418, 370/417, 370/395.5, 710/20
• US Class Current: 370/461
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 63/0227 Filtering policies mail message filtering H04L51/212
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 63/08 for authentication of entities cryptographic mechanisms or cryptographic arrangements for entity authentication H04L9/32

Abstract

A novel network architecture that integrates the functions of an internet protocol (IP) router into a network processing unit (NPU) that resides in a host computer'"'"'s chipset such that the host computer'"'"'s resources are perceived as separate network appliances. The NPU appears logically separate from the host computer even though, in one embodiment, it is sharing the same chip.

Claims

1. A network processing apparatus, said apparatus comprising:

a host central processing unit (CPU);

a system memory;

a media access controller interface (MI) subunit for communicating with at least one media access controller (MAC) to serve as an input and output point for traversal of packets, and to provide an asynchronous boundary interface between a first clock domain of said MAC and a second clock domain of said media access controller interface (MI) subunit;

a host media access controller (HM) for communicating with said media access controller interface (MI) subunit and said host CPU to address packet processing events, wherein said host media access controller (HM) accesses a plurality of push buffers that are stored in system memory to transfer commands or data between said HM and said host CPU;

a sequence processor (SP) that is coupled to the MI and configured to provide automatic decapsulations, decryption, authentication, checksums, and decompression for input packets and compression, checksums, authentication, encryption and encapsulations for output packets; and

an address translation module that is coupled to the SP and configured to perform routing and stateful firewall functions.

2. The apparatus of claim 1, wherein said packet processing events include both router packet processing and host packet processing.

3. The apparatus of claim 1, wherein said plurality of push buffers are organized into at least one buffer pair with one input buffer for storing input commands or data and one output buffer for storing output commands or data.

4. The apparatus of claim 3, wherein said at least one buffer pair of push buffers is used for interfacing with an operating system of said host CPU.

5. The apparatus of claim 3, wherein said at least one buffer pair of push buffers is used for routing packets.

6. The apparatus of claim 3, wherein said at least one buffer pair of push buffers is used for bridging packets.

7. The apparatus of claim 3, wherein said at least one buffer pair of push buffers is used for interfacing with an external media access controller (MAC).

8. The apparatus of claim 1, wherein said plurality of push buffers are organized into at least one triplicate set of push buffers, with one input buffer for storing input commands or data, one output buffer for storing output commands or data and one buffer for storing commands relating to at least one available free buffer.

9. The apparatus of claim 1, wherein said SP is configured to generate random numbers.

10. The apparatus of claim 1, further comprising a first software driver configured to manage communications between said host CPU and said MI for host packet processing.

11. The apparatus of claim 10, further comprising a second software driver configured to manage communications between said MI and other processing units in said network processing system for router packet processing.

12. The apparatus of claim 10, wherein said first software driver selects one push buffer from said plurality of push buffers by detecting how many of said plurality of push buffers that are allocated to store commands or data for consumption by said MI are not empty to produce non-empty push buffers and determining a priority of each non-empty push buffer.

13. Method for providing a network processing unit, said method comprising the steps of:

providing a host central processing unit (CPU);

providing a system memory;

providing a media access controller interface (MI) subunit for communicating with at least one media access controller (MAC) to serve as an input and output point for traversal of packets, and to provide an asynchronous boundary interface between a first clock domain of said MAC and a second clock domain of said media access controller interface (MI) subunit; and

providing a host media access controller (HM) for communicating with said media access controller interface (MI) subunit and said host CPU to address packet processing events, wherein said host media access controller (HM) accesses a plurality of push buffers that are stored in system memory to transfer commands or data between said HM and said host CPU;

providing a sequence processor (SP) that is coupled to the MI and configured to provide automatic decapsulations, decryption, authentication, checksums, and decompression for input packets and compression, checksums, authentication, encryption and encapsulations for output packets; and

providing an address translation module that is coupled to the SP and configured to perform routing and stateful firewall functions.

14. The method of claim 13, wherein said packet processing events include both router packet processing and host packet processing.

15. The method of claim 13, wherein said plurality of push buffers are organized into at least one buffer pair with one input buffer for storing input commands or data and one output buffer for storing output commands or data.

16. The method of claim 15, wherein said at least one buffer pair of push buffers is used for interfacing with an operating system of said host CPU.

17. The method of claim 15, wherein said at least one buffer pair of push buffers is used for routing packets.

18. The method of claim 15, wherein said at least one buffer pair of push buffers is used for bridging packets.

19. The method of claim 15, wherein said at least one buffer pair of push buffers is used for interfacing with an external media access controller (MAC).

20. The method of claim 13, wherein said plurality of push buffers are organized into at least one triplicate set of push buffers, with one input buffer for storing input commands or data, one output buffer for storing output commands or data and one buffer for storing commands relating to at least one available free buffer.

21. The method of claim 20, wherein said at least one buffer pair of push buffers is used for interfacing with an operating system of said host CPU.

22. The method of claim 20, wherein said at least one buffer pair of push buffers is used for routing packets.

23. The method of claim 20, wherein said at least one buffer pair of push buffers is used for bridging packets.

24. The method of claim 20, wherein said at least one buffer pair of push buffers is used for interfacing with an external media access controller (MAC).

25. The method of claim 13, wherein said SP is configured to generate random numbers.

26. The method of claim 13, further comprising the step of providing a first software driver that is configured to manage communications between said host CPU and said MI for host packet processing.

27. The method of claim 26, further comprising the step of providing a second software driver that is configured to manage communications between said MI and other processing units in said network processing system for router packet processing.

28. The method of claim 26, wherein said first software driver selects one push buffer from said plurality of push buffers by detecting how many of said plurality of push buffers that are allocated to store commands or data for consumption by said MI are not empty to produce non-empty push buffers and determining a priority of each non-empty push buffer.