Computer system for accessing initialization data and method therefor

• US 7,325,125 B2
• Filed: 07/29/2003
• Issued: 01/29/2008
• Est. Priority Date: 06/14/1999
• Status: Expired due to Term

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Yeh, Bi-Yun, Wang, Shu-Tzu, Ho, Heng-Chen
• Primary Examiner(s): Perveen; Rehana
• Assistant Examiner(s): Rahman; Fahmida
• Application Number:
  US10/628,562
• Publication Number:
  US 20040059902A1
• Time in Patent Office: 1,645 Days
• Field of Search: 713/1, 713/2
• US Class Current: 713/1
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A method and computer system for accessing initialization data stored in a boot memory space. After the power supply starts up, the south bridge starts up and sends an initiating signal to the north bridge for starting up the north bridge. Once the north bridge has started up, it sends the south bridge a transaction which requests that the south bridge reads the initialization data from the memory space and sends the initialization data to the south bridge. Then, the CPU starts up and operates normally after the CPU receives an initiating signal and the initialization data sent by the north bridge.

Claims

1. A method for accessing initialization data for starting up a central processor unit in a computer system comprising:

providing a non-volatile memory connected to a south-bridge chip, wherein the non-volatile memory includes a first memory space storing routines and code of a basic input/output system (BIOS) and a second memory space storing the initialization data, and wherein the initialization data is excluded from the BIOS and is used for initialization of the central processor unit;

(a) starting up a north-bridge chip that is coupled between the central processor unit and the south-bridge chip;

(b) sending a request from said north-bridge chip to the south-bridge chip in order to access the initialization data from the second memory space of the non-volatile memory;

(c) starting up the central processor unit, wherein step (c) comprises;

receiving said initialization data from the south-bridge chip by said north-bridge chip, and

sending an initiating signal to the central processor unit to set initial values for initialization of the central processor unit based on the received initialization data by said north-bridge chip, wherein no random access memory is used to store said initialization data during step (c).

2. The method according to claim 1 wherein said initialization data is serial initialization packet (“

SIP”

) data of the central processor unit.

3. The method according to claim 2 wherein said initialization data is SIP data for an AMD K7 processor.

4. The method according to claim 1 wherein step (a) comprises starting up the north-bridge chip by said south-bridge chip.

5. The method according to claim 1 wherein step (b) comprises sending a signal from said north bridge chip to said south-bridge chip for requesting said initialization data.

6. The method according to claim 1 further comprising sending said initialization data from said north-bridge chip to the central processor unit of said computer system for starting up the central processor unit.

7. A method for accessing initialization data for starting up a central processor unit in a computer system that also includes a bus, a south-bridge chip connected to the bus, and a north-bridge chip connected between the bus and the central processor unit, the method comprising:

providing a non-volatile memory connected to the south-bridge chip, wherein the non-volatile memory includes a first memory space storing routines and code of a basic input/output system (BIOS) and a second memory space storing the initialization data, and wherein the initialization data is excluded from the BIOS and is used for initialization of the central processor unit;

(a) sending a request from the north-bridge chip to the south-bridge chip in order to access the initialization data from the non-volatile memory;

(b) in response to the request, accessing the second memory space of the non-volatile memory to read out the initialization data by the south-bridge chip;

(c) sending the initialization data from the south-bridge chip to the north-bridge chip; and

(d) activating the central processor units, wherein step (d) comprises;

receiving the initialization data sent from the south-bridge chip by the north-bridge chip,

sending an initiating signal to the central processor unit to set initial values for initialization of the central processor unit based on the initialization data received by the north-bridge chip from the south-bridge chip, wherein no random access memory is used to store said initialization data during step (d).

8. The method of claim 7 further comprising activating the north-bridge chip by sending a first initiating signal from the south-bridge chip to the north-bridge chip before step (a) is conducted.

9. The method of claim 8, further comprising activating the south bridge chip by a power supply before sending the first initiating signal from the south-bridge chip to actuate the north-bridge chip.

10. The method of claim 7 wherein the non-volatile memory is a read only memory.

11. The method of claim 7 wherein the request sent in step (a) is a transaction sent from the north-bridge chip to the south-bridge chip requesting the south-bridge chip to retrieve the initialization data from the non-volatile memory.

12. The method of claim 7 wherein step (d) further includes:

sending the received initialization data to the central processor unit.

13. The method of claim 12 wherein the initialization data includes an initialization ID.

14. The method of claim 12 wherein the initialization data includes serial initialization packet (“

SIP”

) data.

15. A system for accessing initialization data for starting a central processor unit, the system comprising:

a non-volatile memory including;

a first memory space storing routines and code of a basic input/output system (BIOS) and a second memory space storing the initialization data, wherein the initialization data is excluded from the BIOS and is used for initialization of the central processor unit;

a south-bridge chip in direct communication with the non-volatile memory, the south-bridge chip, when requested for the initialization data, accessing the initialization data from the second memory space of the non-volatile memory;

a north-bridge chip, coupled between the south-bridge chip and the central processor unit, the north-bridge chip, when activated, sending a request for the initialization data to the south-bridge chip;

wherein in response to the request from the north-bridge chip for obtaining the initialization data, the south-bridge chip accesses the initialization data from the second memory space and forwards the initialization data to the north-bridge chip for activating the central processor unit;

wherein in response to the initialization data sent from the south-bridge chip, the north-bridge chip sends an initiating signal to the central processor unit to set initial values for initialization of the central processor unit based on the received initialization data from the south-bridge chip in order to activate the central processor unit without using any random access memory to store the initialization data.

16. The system of claim 15 further comprising a power supply for activating the south-bridge chip, wherein the south-bridge chip activates the north-bridge chip when the south-bridge chip is activated.

17. The system of claim 15 wherein the non-volatile memory is a read only memory.

18. The system of claim 17 wherein the non-volatile memory includes a predetermined location for storing the initialization data that is not occupied by the BIOS.

19. The system of claim 15 wherein the initialization data includes an initialization ID.

20. The system of claim 15 wherein the initialization data includes session initialization protocol data.

21. The system of claim 15 wherein the south-bridge chip includes means for:

activating the north-bridge chip;

retrieving the initialization data by the south-bridge chip; and

sending the initialization data to the north-bridge chip.

22. The system of claim 15 wherein the north-bridge chip further includes means for sending an initializing signal to the central processor unit based on the forwarded initialization data.