Phase adjust using relative error

• US 7,325,175 B2
• Filed: 05/04/2005
• Issued: 01/29/2008
• Est. Priority Date: 05/04/2005
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Momtaz, Afshin
• Primary Examiner(s): Ton; David
• Application Number:
  US11/123,355
• Publication Number:
  US 20060253746A1
• Time in Patent Office: 1,000 Days
• Field of Search: 327/280, 327/12, 327/9, 375/371, 714/704, 341/120
• US Class Current: 714/704
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/1075 by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth H03L7/1072 takes precedence
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 7/0058 detection of error based on equalizer tap values
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A system may adjust the times at which data is sampled by separate sampling mechanisms. Here, it may be desirable to ensure that one sampler samples data at substantially the same time as the other sampler. For example, output data from a high speed sampler that samples received data may be compared with an output of an analog to digital converter that samples the received data at a lower data rate. This difference or relative error may be accumulated over a period of time for given values of delay applied to the clock for the analog to digital converter. In this way, a delay value that minimizes the relative error may be selected as a desired delay value.

Claims

1. A method of sampling data comprising:

providing a first sampling of data from at least one data signal;

providing a second sampling of data from the at least one data signal;

processing the first sampling and the second sampling to generate relative error measurements;

accumulating the relative error measurements; and

adjusting at least one of the first sampling and the second sampling in accordance with the accumulated relative error measurements.

2. The method of claim 1 wherein adjusting comprises adjusting phase of at least one clock used to provide the first sampling and the second sampling.

3. The method of claim 1 wherein adjusting comprises providing a phase offset between a plurality of clocks used to provide the first sampling and the second sampling to minimize the relative error measurements.

4. The method of claim 1 wherein providing the first sampling comprises generating a first clock signal at a first clock rate for sampling the least one data signal.

5. The method of claim 4 wherein providing the second sampling comprises generating a second clock signal at a second clock rate for sampling the least one data signal.

6. The method of claim 1 wherein processing the first sampling and the second sampling comprises calculating relative error between data bits from the first sampling and data bits from the second sampling.

7. The method of claim 6 wherein accumulating comprises accumulating the relative error between data bits from the first sampling and data bits from the second sampling.

8. The method of claim 1 wherein processing comprises at least one XOR operation.

9. The method of claim 1 wherein adjusting comprises identifying a phase delay, for at least one clock used to provide the first sampling and the second sampling, that provides a minimum accumulated relative error.

10. The method of claim 9 wherein adjusting comprises setting the phase delay, for the at least one clock used to provide the first sampling and the second sampling, to the identified phase delay.

11. The method of claim 1 wherein at least one adaptation loop in a receiver is adjusted in accordance with the second sampling of data.

12. The method of claim 11 wherein the at least one adaptation loop affects received signal quality in the receiver.

13. A method of aligning sampling clocks comprising:

generating a first clock signal at a first rate;

generating a second clock signal at a second rate;

sampling data from at least one data signal in accordance with the first clock signal;

sampling data from the at least one data signal in accordance with the second clock signal;

calculating relative error between the data sampled in accordance with the first clock signal and the data sampled in accordance with the second clock signal;

accumulating the relative error; and

adjusting a phase of at least one of the first clock signal and the second clock signal in accordance with the accumulated relative error.

14. The method of claim 13 wherein accumulating comprises accumulating relative error measurements associated with each of a plurality of phase settings for at least one of the first clock signal and the second clock signal.

15. The method of claim 13 wherein at least one adaptation loop in a receiver is adjusted in accordance with the data sampled in accordance with the second clock signal.

16. The method of claim 15 wherein the at least one adaptation loop affects signal quality of the data sampled in accordance with the first clock signal.

17. The method of claim 13 wherein the second clock signal is derived from the first clock signal.

18. The method of claim 13 wherein adjusting comprises providing a phase offset between the first clock signal and the second clock signal to minimize the relative error.

19. The method of claim 13 wherein calculating comprises calculating relative error between data bits from the data sampled in accordance with the first clock signal and the data bits from data sampled in accordance with the second clock signal.

20. The method of claim 19 wherein accumulating comprises accumulating the relative error between the data bits.

21. The method of claim 13 wherein calculating comprises at least one XOR operation.

22. The method of claim 13 wherein adjusting comprises identifying a phase delay, for at least one of the first clock signal and the second clock signal, that provides a minimum accumulated relative error.

23. The method of claim 22 wherein adjusting comprises setting phase delay for at least one of the first clock signal and the second clock signal to the identified phase delay.

24. A communications system comprising:

a decision feedback equalizer configured to generate a soft decision signal and a hard decision signal in accordance with a received signal;

at least one clock generator configured to generate a first clock signal in accordance with the hard decision signal and configured to generate a second clock signal in accordance with the first clock signal and a delay adjust signal;

a retimer configured to sample the hard decision signal in accordance with the first clock signal to generate a retimed signal;

an analog to digital converter configured to sample the soft decision signal in accordance with the second clock signal to generate a sampled signal; and

a relative error circuit configured to generate the delay adjust signal in accordance with the retimed signal and the sampled signal.

25. The system of claim 24 wherein the relative error circuit is configured to generate relative error data in accordance with the retimed signal and the sampled signal.

26. The system of claim 25 wherein the relative error circuit comprises at least one data memory for accumulating the relative error data.

27. The system of claim 24 wherein the analog to digital converter comprises a sample and hold circuit.

28. The system of claim 24 wherein the at least one clock generator comprises a clock and data recovery circuit.

29. The system of claim 24 wherein the at least one clock generator comprises a delay lock loop.

30. The system of claim 29 wherein the delay lock loop comprises at least one variable delay element configured to be controlled in accordance with the delay adjust signal.

31. The system of claim 29 wherein the delay lock loop comprises at least one fixed delay element.

32. The system of claim 24 comprising at least one adaptation loop for adjusting signal quality of the received signal.

33. The system of claim 32 wherein the at least one adaptation loop generates coefficients in accordance with the sampled signal to adjust the signal quality.

34. The system of claim 24 comprising at least one adaptation loop for generating coefficients for the decision feedback equalizer.

35. The system of claim 34 wherein the at least one adaptation loop generates feedback coefficients in accordance with the sampled signal.

36. A method of adjusting clock delay in a system comprising:

temporarily setting a phase delay associated with at least one clock signal to a plurality of delay values;

generating a relative error when the phase delay is temporarily set to each of the delay values;

accumulating the relative error generated for each of the delay values;

identifying at least one delay value associated with a minimum accumulated relative error; and

setting the phase delay in accordance with the identified at least one delay value.

37. The method of claim 36 comprising repeatedly enabling a clock delay adaptation loop to perform the temporarily setting, the generating and the accumulating.

38. The method of claim 37 comprising disabling at least one other adaptation loop when the clock delay adaptation loop is enabled.

39. The method of claim 38 wherein the at least one other adaptation loop adapts based on data sampled in accordance with the at least one clock signal.

40. The method of claim 37 comprising repeatedly disabling the clock delay adaptation loop to enable at least one other adaptation loop.

41. The method of claim 36 wherein:

the at least one clock signal comprises two clock signals; and

generating comprises processing data bits sampled in accordance with each of the two clock signals.

42. The method of claim 41 wherein processing data comprises determining whether a data bit sampled in accordance with a first one of the two clock signals has the same value as a data bit sampled in accordance with a second one of the two clock signals.

43. The method of claim 36 wherein accumulating comprises separately accumulating relative error for each of the delay values.

44. The method of claim 43 wherein identifying comprises comparing the accumulated relative error for each of the delay values to identify at least one delay value associated with the minimum accumulated relative error.