Gettering using voids formed by surface transformation

• US 7,326,597 B2
• Filed: 06/27/2005
• Issued: 02/05/2008
• Est. Priority Date: 07/21/2003
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Geusic, Joseph E.
• Primary Examiner(s): MANDALA, MICHELLE
• Application Number:
  US11/167,894
• Publication Number:
  US 20050250274A1
• Time in Patent Office: 953 Days
• Field of Search: 438/143, 438/402, 438/471, 438/FOR.144, 257/E21.318
• US Class Current: 438/143
• CPC Class Codes: H01L 21/3223 using cavities formed by hydrogen or noble gas ion implantation
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: Y10S 257/913 with means to absorb or localize unwanted impurities or defects from semiconductors, e.g. heavy metal gettering

Abstract

One aspect of this disclosure relates to a method for creating a gettering site in a semiconductor wafer. In various embodiments, a predetermined arrangement of a plurality of holes is formed in the semiconductor wafer through a surface of the wafer. The wafer is annealed such that the wafer undergoes a surface transformation to transform the arrangement of the plurality of holes into a predetermined arrangement of at least one empty space of a predetermined size within the wafer to form the gettering site. One aspect relates to a semiconductor wafer. In various embodiments, the wafer includes at least one device region, and at least one gettering region located proximate to the at least one device region. The gettering region includes a precisely-determined arrangement of a plurality of precisely-formed voids that are formed within the wafer using a surface transformation process. Other aspects and embodiments are provided herein.

Claims

1. A method for forming a transistor, comprising:

forming a proximity gettering region to be proximate to a crystalline semiconductor region in a wafer, the proximity gettering region including a precise arrangement of precisely-formed voids to getter impurities from the crystalline semiconductor region;

forming a gate dielectric over the crystalline semiconductor region;

forming a gate over the gate dielectric; and

forming a first diffusion region and a second diffusion region in the crystalline semiconductor region, the first and second diffusion regions being separated by a channel region formed in the crystalline semiconductor region between the gate and the proximity gettering region.

2. The method of claim 1, wherein forming a proximity gettering region to be proximate to a crystalline semiconductor region in a wafer includes forming a plurality of holes into the wafer with a predetermined width and with a predetermined depth from a surface of the wafer, and wherein the predetermined width and the predetermined depth of the holes are factors in determining a size and a depth of the voids in the proximity gettering region.

3. The method of claim 1, wherein the precisely-formed voids include a sphere-shaped void.

4. The method of claim 1, wherein the precisely-formed voids include a pipe-shaped void.

5. The method of claim 1, wherein the precisely-formed voids include a plate-shaped void.

6. The method of claim 1, wherein the crystalline semiconductor region includes a crystalline silicon region.

7. A method for forming a semiconductor structure, comprising:

forming a proximity gettering region to be proximate to a crystalline semiconductor region in a wafer, the proximity gettering region including a predetermined arrangement of precisely-formed voids to getter impurities from the crystalline semiconductor region; and

performing semiconductor fabrication processes in the crystalline semiconductor region to form a semiconductor device proximate to the gettering region.

8. The method of claim 7, wherein the semiconductor structure includes a memory device, and performing semiconductor fabrication processes includes performing processes to form the memory device proximate to the gettering region, including:

forming a memory array in the crystalline semiconductor region;

forming a plurality of word lines for the memory array;

forming a plurality of bit lines for the memory array; and

forming control circuitry, including forming word line select circuitry and bit line select circuitry for use to select a number of memory cells for writing and reading operations.

9. The method of claim 7, wherein forming a proximity gettering region includes:

forming a predetermined arrangement of a plurality of holes in a wafer through a surface of the wafer; and

annealing the wafer to transform the arrangement of the plurality of holes into the predetermined arrangement of precisely-formed voids.

10. The method of claim 7, wherein the precisely-formed voids include a sphere-shaped void.

11. The method of claim 7, wherein the precisely-formed voids include a pipe-shaped void.

12. The method of claim 7, wherein the precisely-formed voids include a plate-shaped void.

13. A method for forming a transistor, comprising:

forming a proximity gettering region to be proximate to a crystalline semiconductor region in a wafer, the proximity gettering region including a precise arrangement of sphere-shaped voids to getter impurities from the crystalline semiconductor region, wherein forming a proximity gettering region includes;

forming a predetermined arrangement of a plurality of holes in the wafer through a surface of the wafer; and

annealing the wafer to transform the predetermined arrangement of the plurality of holes into the arrangement of sphere-shaped voids to form the proximity gettering region in the wafer;

forming a gate dielectric over the crystalline semiconductor region;

forming a gate over the gate dielectric; and

forming a first diffusion region and a second diffusion region in the crystalline semiconductor region, the first and second diffusion regions being separated by a channel region formed in the crystalline semiconductor region between the gate and the proximity gettering region.

14. The method of claim 13, wherein each void has an interior surface with dangling bonds.

15. The method of claim 13, wherein the wafer includes a bulk semiconductor wafer.

16. The method of claim 13, wherein the wafer includes a semiconductor-on-insulator (SOI) wafer.

17. A method for forming a transistor, comprising:

forming a proximity gettering region to be proximate to a crystalline semiconductor region in a wafer, the proximity gettering region including a precise arrangement of pipe-shaped voids to getter impurities from the crystalline semiconductor region, wherein forming a proximity gettering region includes;

forming a predetermined arrangement of a plurality of holes in the wafer through a surface of the wafer; and

annealing the wafer to transform the predetermined arrangement of the plurality of holes into the arrangement of pipe-shaped voids to form the proximity gettering region in the wafer;

forming a gate dielectric over the crystalline semiconductor region;

forming a gate over the gate dielectric; and

forming a first diffusion region and a second diffusion region in the crystalline semiconductor region, the first and second diffusion regions being separated by a channel region formed in the crystalline semiconductor region between the gate and the proximity gettering region.

18. The method of claim 17, wherein each void has an interior surface with dangling bonds.

19. The method of claim 17, wherein the wafer includes a bulk semiconductor wafer.

20. The method of claim 17, wherein the wafer includes a semiconductor-on-insulator (SOI) wafer.

21. A method for forming a transistor, comprising:

forming a proximity gettering region to be proximate to a crystalline semiconductor region in a wafer, the proximity gettering region including a precise arrangement of plate-shaped voids to getter impurities from the crystalline semiconductor region, wherein forming a proximity gettering region includes;

forming a predetermined arrangement of a plurality of holes in the wafer through a surface of the wafer; and

annealing the wafer to transform the predetermined arrangement of the plurality of holes into the arrangement of plate-shaped voids to form the proximity gettering region in the wafer;

forming a gate dielectric over the crystalline semiconductor region;

forming a gate over the gate dielectric; and

forming a first diffusion region and a second diffusion region in the crystalline semiconductor region, the first and second diffusion regions being separated by a channel region formed in the crystalline semiconductor region between the gate and the proximity gettering region.

22. The method of claim 21, wherein each void has an interior surface with dangling bonds.

23. The method of claim 21, wherein the wafer includes a bulk semiconductor wafer.

24. The method of claim 21, wherein the wafer includes a semiconductor-on-insulator (SOI) wafer.

25. A method for forming a transistor, comprising:

forming a proximity gettering region to be proximate to a crystalline semiconductor region in a wafer, the proximity gettering region including a precise arrangement of voids to getter impurities from the crystalline semiconductor region, wherein forming a proximity gettering region includes;

forming a predetermined arrangement of a plurality of holes in the wafer through a surface of the wafer, including forming each of the plurality of holes with a predetermined length and a predetermined diameter; and

annealing the wafer to transform the predetermined arrangement of the plurality of holes with the predetermined length and the predetermined diameter into the arrangement of voids determined by the length and the diameter of the holes to form the proximity gettering region in the wafer;

forming a gate dielectric over the crystalline semiconductor region;

forming a gate over the gate dielectric; and

forming a first diffusion region and a second diffusion region in the crystalline semiconductor region, the first and second diffusion regions being separated by a channel region formed in the crystalline semiconductor region between the gate and the proximity gettering region.

26. The method of claim 25, wherein forming each of the plurality of holes includes forming each of the plurality of holes with a length that is approximately equal to an integer of a critical length (λ

_C) dependent on a hole radius (R_C).

27. The method of claim 25, wherein forming each of the plurality of holes includes forming each of the plurality of holes with a length that is not approximately equal to an integer of a critical length (λ

_C) dependent on a hole radius (R_C), the method further comprising polishing a top surface of the wafer after annealing in preparation to form the gate dielectric.