Method of manufacturing a semiconductor device and semiconductor device obtainable with such a method

• US 7,326,620 B2
• Filed: 03/11/2005
• Issued: 02/05/2008
• Est. Priority Date: 03/12/2004
• Status: Active Grant

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International), NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International), Koninklijke Philips N.V.
• Inventors: Pawlak, Bartlomiej Jan
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US11/077,973
• Publication Number:
  US 20050236663A1
• Time in Patent Office: 1,061 Days
• Field of Search: 438/238, 438/582, 438/283, 257/E21.442
• US Class Current: 438/283
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of manufacturing a semiconductor device comprising a dual gate field effect transistor is disclosed, in which method a semiconductor body with a surface and of silicon is provided with a source region and a drain region of a first conductivity type and with a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region and with a first gate region separated from the channel region by a first gate dielectric and situated on one side of the channel region and with a second gate region separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, and wherein both gate regions are formed within a trench formed in the semiconductor body.

Claims

1. A method of manufacturing a semiconductor device comprising a dual gate field effect transistor, comprising:

providing a semiconductor body of silicon with a surface, a source region and a drain region of a first conductivity type, a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region;

forming a first gate within a first trench, separated from the channel region by a first gate dielectric and situated on one side of the channel region;

forming a second gate within a second trench, separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region,

wherein both gates are formed within a third trench formed in the semiconductor body,

wherein the channel region is formed by the part of the semiconductor body between the first and second trench, and

wherein the source and drain regions are formed by implantation at the surface of the semiconductor body.

3. The method as claimed in claim 1, wherein the source and drain regions are formed by depositing a strip-shaped mask layer on the surface of the semiconductor body which bridges the two regions where the trenches are formed or to be formed, after which dopants of the first conductivity type are introduced into the semiconductor body on both sides of the strip-shaped mask layer.

4. The method as claimed in claim 1, further comprising forming two dual gate transistors which are proximate each other in the semiconductor body by forming a fourth trench in the semiconductor body of which the second trench forms a common gate for the two dual gate transistors.

5. The method as claimed in claim 4, wherein a first of the two dual gate transistors is formed as an npn transistor and a second of the two dual gate transistors is formed as a pnp transistor.

6. The method as claimed in claim 1, wherein the source and drain regions of the dual gate transistor are separated from the semiconductor body on a side opposite to the channel region by the third trench.

7. The method as claimed in claim 1, wherein the dual gate transistor is formed together with other conventional transistors made by conventional CMOS technology.

2. A method of manufacturing a semiconductor device comprising a dual gate field effect transistor, comprising:

providing a semiconductor body of silicon with a surface, a source region and a drain region of a first conductivity type, a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region;

forming a first gate within a first trench, separated from the channel region by a first gate dielectric and situated on one side of the channel region;

forming a second gate within a second trench, separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region,

wherein both gates are formed within a third trench formed in the semiconductor body,

wherein the channel region is formed by the part of the semiconductor body between the first and second trench, and

wherein the first and second trenches are formed in parallel in the surface of the semiconductor body and trench walls are provided with a dielectric layer and are filled with a conductive material by depositing a conductive layer on the semiconductor body, and wherein selected portions on top of the surface of the semiconductor body are removed by chemical mechanical polishing.

8. The method as claimed in claim 2, wherein the conductive layer comprises metal.

9. A method of manufacturing a semiconductor device comprising a dual gate field effect transistor, comprising:

providing a semiconductor body of silicon with a surface, a source region and a drain region of a first conductivity type, a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region;

forming a first gate within a first trench, separated from the channel region by a first gate dielectric and situated on one side of the channel region;

forming a second gate within a second trench, separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, wherein the first and second trenches are formed in parallel in the surface of the semiconductor body and trench walls are provided with a dielectric layer and are filled with a conductive material by depositing a conductive layer on the semiconductor body, and wherein selected portions on top of the surface of the semiconductor body are removed;

wherein the first and second gates are formed within a third trench formed in the semiconductor body,

wherein the channel region is formed by the part of the semiconductor body between the first and second trench, and

wherein the source and drain regions are formed by implantation at the surface of the semiconductor body.

10. The method of claim 9, wherein the selected portions on top of the surface of the semiconductor body are removed by chemical mechanical polishing.

11. A method of manufacturing a semiconductor device comprising a dual gate field effect transistor, comprising:

providing a semiconductor body;

forming a source region and a drain region of a first conductivity type in the semiconductor body, wherein the source region and the drain region are formed by implantation at opposite sides along a length of the semiconductor body;

forming a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region;

forming a first gate within a first trench, separated from the channel region by a first gate dielectric and situated on one side of the channel region;

forming a second gate within a second trench, separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, wherein the second gate is separated from the first gate, wherein the first and second gates are formed within a third trench formed in the semiconductor body, and wherein the channel region is formed by the part of the semiconductor body between the first and second trenches.

12. The method of claim 11, wherein the first and second trenches are formed in parallel in the semiconductor body and trench walls are provided with a dielectric layer and are filled with a conductive material by depositing a conductive layer on the semiconductor body, and wherein selected portions on top of the semiconductor body are removed.

13. The method of claim 12, wherein the selected portions on top of the semiconductor body are removed by chemical mechanical polishing.