Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

• US 7,326,634 B2
• Filed: 03/22/2005
• Issued: 02/05/2008
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Cea, Stephen M., Lindert, Nick
• Primary Examiner(s): Parker; Kenneth
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US11/088,035
• Publication Number:
  US 20050218438A1
• Time in Patent Office: 1,050 Days
• Field of Search: 438/128, 438/284, 438/587, 438/598, 438/588, 438/157, 257/202, 257/250, 257/347, 257/401
• US Class Current: 438/585
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A method of forming a semiconductor device comprising:

forming a pair of isolation regions in a semiconductor substrate, said pair of isolation regions defining an active substrate region in said semiconductor substrate therebetween, said isolation region extending above said substrate;

forming a semiconductor film on said active region of said semiconductor substrate between said pair of isolation regions;

etching back said isolation regions to form a semiconductor body from said semiconductor film wherein said semiconductor body has a top surface and a pair of laterally opposite sidewalls;

forming a semiconductor capping layer on said top surface and said sidewalls of said semiconductor body;

forming a gate dielectric layer over said capping layer formed on said sidewalls of said top surface of said semiconductor body;

forming a gate electrode having a pair of laterally opposite sidewalls on and around said gate dielectric layer; and

forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.

2. The method of claim 1 wherein said semiconductor film is selectively grown from said active region of said semiconductor substrate.

3. The method of claim 1 wherein said capping layer is selectively grown from said semiconductor body.

4. The method of claim 1 wherein said isolation regions are etched back with a wet etchant.

5. The method of claim 1 wherein said semiconductor capping layer has a tensile stress.

6. The method of claim 5 wherein said semiconductor capping layer has a greater tensile stress on the sidewalls of said semiconductor body than on the top surface of said semiconductor body.

7. The method of claim 5 wherein said source/drain regions are n type conductivity.

8. The method of claim 1 wherein said semiconductor substrate is a silicon substrate and wherein said semiconductor body is a silicon germanium alloy and wherein said semiconductor capping layer is silicon.

9. The method of claim 1 wherein said semiconductor capping layer has a compressive stress.

10. The method of claim 9 wherein said semiconductor capping layer has a greater compressive stress on the sidewalls than on the top surface of said semiconductor body.

11. The method of claim 9 wherein said semiconductor substrate is a monocrystalline silicon substrate, wherein said semiconductor body comprises a silicon-carbon alloy and wherein said semiconductor capping layer an expitaxial silicon.

12. The method of claim 9 wherein said source/drain regions are p type conductivity.

13. A method of forming a semiconductor device comprising:

forming a pair of spaced apart isolation regions in a semiconductor substrate, said spaced apart isolation regions defining an active substrate area in said substrate wherein said isolation regions extend above said active substrate area;

forming a semiconductor film on said active area of said substrate between said isolation regions;

forming a first capping layer on said top surface of said semiconductor film between said isolation regions;

etching back said isolation regions to form a semiconductor body having a top surface with said first capping layer and a pair of laterally opposite sidewalls;

forming a second capping layer on said first capping layer on the top surface of said semiconductor body and on said sidewalls of said semiconductor body;

forming a gate dielectric layer on said second capping layer on said first capping layer on said semiconductor body and on said second capping layer on said sidewalls of said semiconductor body;

forming a gate electrode having a pair of laterally opposite sidewalls on and around said gate dielectric layer; and

forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode.

14. The method of claim 13 wherein said first and second capping layer are epitaxial silicon and wherein said semiconductor body is a silicon germanium alloy and wherein said semiconductor substrate is a silicon monocrystalline substrate.

15. The method of claim 13 wherein said first and second capping layer are epitaxial silicon, wherein said semiconductor body is a silicon-carbon alloy and wherein said semiconductor substrate is a silicon monocrystalline substrate.

16. The method of claim 13 wherein said first and second semiconductor capping layers have a tensile stress.

17. The method of claim 13 wherein said first and second semiconductor capping layers have a compressive stress.

18. The method of claim 13 wherein said semiconductor film has a different lattice structure than said semiconductor substrate so that said semiconductor film has a stress formed therein.