Resistive memory device with a treated interface

• US 7,326,979 B2
• Filed: 09/19/2003
• Issued: 02/05/2008
• Est. Priority Date: 08/02/2002
• Status: Expired due to Fees

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Hsia, Steve Kuo-Ren, Chevallier, Christophe, Kinney, Wayne, Ward, Edmond, Rinerson, Darrell, Sanchez, John E. Jr., Longcor, Steven W.
• Primary Examiner(s): Parker; Kenneth
• Assistant Examiner(s): KRAIG, WILLIAM F
• Application Number:
  US10/665,882
• Publication Number:
  US 20040159828A1
• Time in Patent Office: 1,600 Days
• Field of Search: 257/295, 257/379, 257/536, 257/537, 257/E27.006, 257/E21.294, 257/E21.495, 365/45, 365/46, 365/100, 365/148, 365/158, 365/159, 438/385
• US Class Current: 257/295
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/043 by implantation
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/841 Electrodes
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

A multi-resistive state element that uses a treated interface is provided. A memory plug includes at least two electrodes that sandwich a multi-resistive state element. Using different treatments on both electrode/multi-resistive state element interfaces improves the memory properties of the entire memory device.

Claims

1. A resistive memory device comprising:

a conductive bottom electrode having a top surface;

a multi-resistive state element having a top surface and a bottom surface, the bottom surface of the multi-resistive state element arranged on top of and in direct physical contact with the top surface of the conductive bottom electrode, the multi-resistive state element having a substantially crystalline layer that, while substantially maintaining its substantially crystalline structure has a modifiable resistance;

a conductive top electrode having a bottom surface and arranged on top of and in direct physical contact with the top surface of the multi-resistive state element, wherein the resistance of the resistive memory device may be changed by applying a first voltage having a first polarity across the conductive electrodes and reversibly changed by applying a second voltage having a second polarity across the conductive electrodes;

a top interface created by the direct physical contact between the bottom surface of the top electrode and the top surface of the multi-resistive state element; and

a bottom interface created by the direct physical contact between the top surface of the bottom electrode and the bottom surface of the multi-resistive state element, at least one of the top interface or the bottom interface includes at least one treatment primarily directed towards changing properties of the at least one interface,

wherein the at least one treatment is an exposure to a gas,

wherein the exposure to the gas causes a chemical reaction in the multi-resistive state material, and

whereby the properties of the at least one interface are changed by the at least one treatment.

6. The resistive memory device of claim 1, wherein:

the substantially crystalline layer is fabricated to be polycrystalline.

7. The resistive memory device of claim 1, wherein:

the substantially crystalline layer is fabricated to be a perovskite.

8. The resistive memory device of claim 7, wherein:

the treatment, to which the at least one interface is subjected, is directed towards changing properties of the perovskite.

2. A resistive memory device comprising:

a conductive bottom electrode having a top surface;

a multi-resistive state element having a top surface and a bottom surface, the bottom surface of the multi-resistive state element arranged on top of and in direct physical contact with the top surface of the conductive bottom electrode, the multi-resistive state element having a substantially crystalline layer that, while substantially maintaining its substantially crystalline structure, has a modifiable resistance;

a conductive top electrode having a bottom surface and arranged on top of and in direct physical contact with the top surface of the multi-resistive state element, wherein the resistance of the resistive memory device may be changed by applying a first voltage having a first polarity across the conductive electrodes and reversibly changed by applying a second voltage having a second polarity across the conductive electrodes;

a top interface created by the direct physical contact between the bottom surface of the top electrode and the top surface of the multi-resistive state element; and

a bottom interface created by the direct physical contact between the top surface of the bottom electrode and the bottom surface of the multi-resistive state element, at least one of the top interface or the bottom interface includes at least one treatment primarily directed towards changing properties of the at least one interface,

wherein the at least one treatment is caused by a chemical reaction between one of the conductive electrodes and the multi-resistive state element, and

whereby the properties of the at least one interface are changed by the at least one treatment.

3. The resistive memory device of claim 2, wherein:

an anneal process is a catalyst for the chemical reaction.

4. The resistive memory device of claim 2, wherein:

an exposure to a gas is a catalyst for the chemical reaction.

5. A resistive memory device comprising:

a conductive bottom electrode having a top surface;

a multi-resistive state element having a top surface and a bottom surface, the bottom surface of the multi-resistive state element arranged on top of and in direct physical contact with the ton surface of the conductive bottom electrode, the multi-resistive state element having a substantially crystalline layer that, while substantially maintaining its substantially crystalline structure, has a modifiable resistance;

a conductive top electrode having a bottom surface and arranged on top of and in direct physical contact with the top surface of the multi-resistive state element, wherein the resistance of the resistive memory device may be changed by applying a first voltage having a first polarity across the conductive electrodes and reversibly changed by applying a second voltage having a second polarity across the conductive electrodes;

a top interface created by the direct physical contact between the bottom surface of the top electrode and the top surface of the multi-resistive state element; and

a bottom interface created by the direct physical contact between the top surface of the bottom electrode and the bottom surface of the multi-resistive state element, at least one of the top interface or the bottom interface includes at least one treatment primarily directed towards changing properties of the at least one interface,

wherein the at least one treatment is caused by a bombardment by inert ions, and

whereby the properties of the at least one interface are changed by the at least one treatment.