Trench MIS device having implanted drain-drift region and thick bottom oxide

• US 7,326,995 B2
• Filed: 06/22/2005
• Issued: 02/05/2008
• Est. Priority Date: 07/03/2001
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Owyang, King
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/158,382
• Publication Number:
  US 20050236665A1
• Time in Patent Office: 958 Days
• Field of Search: 257/330, 257/332, 257/333, 257/401, 257/411
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. Therefore, in embodiments where the thermal budget of the process is limited following the implant of the drain-drift region, the PN junctions between the drain-drift region and the epitaxial layer are self-aligned with the edges of the thick bottom oxide. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The relatively flat dopant profile in the channel region provides an increased punchthrough voltage and low threshold voltage.

Claims

1. A trench MIS device comprising:

a substrate of a first conductivity type;

an epitaxial layer of a second conductivity type on the substrate, an interface between the epitaxial layer and the substrate forming a first PN junction;

a trench extending into the epitaxial layer from a surface of the epitaxial layer, the trench having a bottom in the epitaxial layer above the interface between the substrate and the epitaxial layer;

a gate positioned in the trench;

a gate insulating layer along a sidewall of the trench;

a bottom insulating layer on a bottom of the trench, the bottom insulating layer being thicker than the gate insulating layer and abutting the gate insulating layer, the gate being electrically insulated from the epitaxial layer by the gate insulating layer and the bottom insulating layer;

a drain-drift region of the first conductivity type in the epitaxial layer, the drain-drift region extending between the trench and the interface between the epitaxial layer and the substrate, the drain-drift region forming a second PN junction with a remaining portion of the epitaxial layer, the second PN junction extending between the trench and the first PN junction, the second PN junction being aligned with a location where the bottom insulating layer and the gate insulating layer meet.

2. The trench MIS device of claim 1 wherein the second PN junction is concave with respect to the interior of the drain-drift region.

3. The trench MIS device of claim 1 wherein the second PN junction extends between the substrate and the sidewall of the trench.

4. The trench MIS device of claim 1 wherein the trench MIS device comprises a trench MOSFET, the trench MOSFET comprising a seurce regien located adjacent the sidewall of the trench and the surface of the epitaxial layer.

5. The trench MIS device of claim 4 comprising a threshold adjust implant region of the second conductivity type located in the epitaxial layer adjacent the sidewall of the trench.

6. The trench MIS device of claim 5 comprising a body region of the second conductivity type located in the epitaxial layer adjacent the source region and the sidewall of the trench, the body region being doped more heavily than the epitaxial layer.

7. The trench MIS device of claim 1 wherein the drain-drift region extends downward from the trench to the interface between the epitaxial layer and the substrate, the drain-drift region being bordered on both sides by the remaining portion of the epitaxial layer.

8. The trench MIS device of claim 7 wherein a concentration of the dopant of the first conductivity in the drain-drift region increases monotonically with increasing distance below the bottom of the trench.

9. The trench MIS device of claim 1 wherein the drain-drift region includes a more heavily doped region of the first conductivity type abutting the bottom of the trench but not extending to the interface between the epitaxial layer and the substrate.

10. The trench MIS device of claim 1 wherein the second PN junction extends between the bottom of the trench and the first PN junction.

11. The trench MIS device of claim 1 wherein the second PN junction extends between the sidewall of the trench and the first PN junction.

12. The trench MIS device of claim 1 wherein the trench has a rounded corner between the bottom and the sidewall of the trench, the second PN junction extending between the rounded corner of the trench and the first PN junction.