Effective I/O ESD protection device for high performance circuits

• US 7,326,998 B1
• Filed: 07/19/2005
• Issued: 02/05/2008
• Est. Priority Date: 11/14/2002
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Shih, Chih-Ching, Huang, Cheng-Hsiung, O, Hugh Sungki, Liu, Yow-Juang Bill
• Primary Examiner(s): Menz; Douglas M.
• Application Number:
  US11/185,609
• Time in Patent Office: 931 Days
• Field of Search: 257/355, 257/365
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0277 involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

An integrated circuit is disclosed comprising at least one I/O pull-down device for protecting I/O logic circuits from electrostatic discharge (ESD). The turn-on voltage of the parasitic bipolar transistor in the I/O pull-down device is lowered by forming under a portion of the lightly doped drain (LDD) region of a first conductivity type of a conventional MOS transistor a second region of a second conductivity type. A P-N junction is formed between the second region and the source/drain regions. The turn-on voltage of the parasitic bipolar transistor in the I/O pull-down device can be reduced by at least 3 volts from that of a comparable device that does not practice the invention and can be varied by varying the concentration of the dopant. A method for forming the circuit including a process for recovering the current of the I/O pull-down device and its advantages are also disclosed.

Claims

1. An integrated circuit comprising at least one I/O logic circuit and at least one electrostatic discharge (ESD) protection device formed in a substrate having a first conductivity type, said logic circuit and said ESD protection device each comprising:

a gate on the substrate and insulated therefrom,

first and second heavily doped regions having a second conductivity type located in the substrate on opposite sides of the gate and forming source and drain regions; and

first and second lightly doped drain (LDD) regions having a second conductivity type located in the substrate on opposite sides of the gate and extending from one of the heavily doped regions toward the other heavily doped region;

wherein said ESD protection circuit further comprises a region of first conductivity type located under a portion of the LDD regions of the ESD protection device but not under any portion of the first and second LDD regions of the I/O logic circuit, said region of first conductivity type forming a P-N junction with an adjacent source/drain region under no more than approximately 50% of the width of the LDD regions.

2. The integrated circuit of claim 1 wherein the first and second heavily doped regions and the first LDD region have N-type conductivity.

3. The integrated circuit of claim 1 wherein the P-N junction is formed under a central portion of the first LDD region.

4. The integrated circuit of claim 1 wherein the P-N junction is formed under approximately 25% of the width of the LDD regions.

5. An integrated circuit comprising at least one I/O logic circuit and at least one electrostatic discharge (ESD) protection device formed in a substrate having a first conductivity type, said logic circuit and said ESD protection device each comprising:

a gate on the substrate and insulated therefrom;

first and second heavily doped N-type regions in the substrate on opposite side of the gate and forming source and drain regions;

a first N-type lightly doped drain (LDD) region extending from the first N-type region toward the gate; and

a second N-type LDD region extending from the second N-type region toward the gate

wherein said ESD protection circuit further comprises a P-type region located under a portion of the first N-type LDD region of the ESD protection device but not under any portion of the LDD regions of the I/O logic circuit, said P-type region forming a P-N junction with the first heavily doped N-type region under no more than approximately 50% of the width of the LDD region.

6. The integrated circuit of claim 5 wherein the P-type region is under both the first and the second N-type LDD regions.

7. The integrated circuit of claim 5 wherein the P-type region is formed under a central region of the first N-type lightly doped drain region.

8. The integrated circuit of claim 5 wherein the P-N junction is formed under approximately 25% of the width of the LDD regions.

9. An electrostatic discharge (ESD) protection device formed in a substrate having a first conductivity type, said device comprising:

a gate on a substrate and insulated therefrom;

first and second heavily doped regions having a second conductivity type located in the substrate on opposite sides of the gate and forming source and drain regions;

first and second lightly doped drain (LDD) regions having a second conductivity type located in the substrate on opposite sides of the gate and extending from one of the heavily doped regions toward the other heavily doped region; and

a region of first conductivity located under no more than approximately 50% of the width of the LDD regions and forming a P-N junction with an adjacent source/drain region.

10. The ESD device of claim 9 wherein the first and second heavily doped regions and the LDD regions have N-type conductivity.

11. The ESD device of claim 9 wherein the P-N junction is formed under a central portion of the LDD regions.

12. The ESD device of claim 9 wherein the P-N junction is formed under approximately 25% of the width of the LDD regions.