Inductors for integrated circuits

• US 7,327,010 B2
• Filed: 03/27/2006
• Issued: 02/05/2008
• Est. Priority Date: 11/23/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gardner, Donald S.
• Primary Examiner(s): Nguyen; Tuan H.
• Application Number:
  US11/390,020
• Publication Number:
  US 20060163695A1
• Time in Patent Office: 680 Days
• Field of Search: 257/528, 257/531, 438/381, 336/200
• US Class Current: 257/528
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/0046 with a conductive path having a bridge
• CPC Class Codes: H01F 41/042 by thin film techniques
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

An inductor for an integrated circuit or integrated circuit package comprises a three-dimensional structure. In one embodiment the inductor is arranged on an integrated circuit substrate in at least two rows, each row comprising upper segments and lower segments, with the upper segments being longer than the lower segments. The upper segments in a first row are offset 180 degrees from those in an adjoining row to provide greater coupling of magnetic flux. The materials and geometry are optimized to provide a low resistance inductor for use in high performance integrated circuits. In another embodiment the inductor is arranged on an integrated circuit package substrate. Also described are methods of fabricating the inductor on an integrated circuit or as part of an integrated circuit package.

Claims

1. An integrated circuit package comprising an inductive element fabricated by:

forming at least one multi-level inductive element on a substrate in a serpentine pattern comprising at least two rows, wherein each row comprises upper conductive segments and lower conductive segments, and in at least one row the upper conductive segments are longer than the lower conductive segments; and

mounting an integrated circuit on the substrate,

wherein, in forming, the at least one multi-level inductive element comprises at least one layer of magnetic material.

2. The integrated circuit package recited in claim 1 wherein, in forming, the upper conductive segments and the lower conductive segments are arranged in a stepped manner.

3. The integrated circuit package recited in claim 1 wherein, in forming, the upper conductive segments and the lower conductive segments are arranged in an undulating manner.

4. The integrated circuit package recited in claim 1 wherein, in forming, the upper conductive segments in one row are offset 180 degrees from the upper conductive segments in an adjacent row.

5. An integrated circuit component comprising an inductive element fabricated by:

forming a substrate; and

forming at least one multi-level inductive element on the substrate in a serpentine pattern comprising at least two rows, wherein each row comprises upper conductive segments and lower conductive segments, and in at least one row the upper conductive segments are longer than the lower conductive segments,

wherein, in forming the at least one multi-level inductive element, the at least one multi-level inductive element comprises at least one layer of magnetic material.

6. The integrated circuit component recited in claim 5 wherein, in forming the substrate, the substrate is formed of material from the group consisting of silicon, germanium, gallium arsenide, polyimide, organic material, a printed circuit board, glass, quartz, and ceramic.

7. The integrated circuit component recited in claim 5 wherein, in forming the at least one multi-level inductive element, the upper conductive segments and the lower conductive segments are arranged in a stepped manner.

8. The integrated circuit component recited in claim 5 wherein, in forming the at least one multi-level inductive element, the upper conductive segments and the lower conductive segments are arranged in an undulating manner.

9. The integrated circuit component recited in claim 5 wherein, in forming the at least one multi-level inductive element, the upper conductive segments in one row are offset 180 degrees from the upper conductive segments in an adjacent row.

10. An integrated circuit package comprising an inductive element fabricated by:

forming a substrate;

forming at least one multi-level inductive element on the substrate in a serpentine pattern comprising at least two rows, wherein each row comprises upper conductive segments and lower conductive segments, and in at least one row the upper conductive segments are longer than the lower conductive segments; and

mounting an integrated circuit on the substrate,

wherein, in forming the at least one multi-level inductive element, the at least one multi-level inductive element comprises at least one layer of magnetic material.

11. The integrated circuit package recited in claim 10 wherein, in forming the substrate, the substrate is formed of material from the group consisting of silicon, germanium, gallium arsenide, polyimide, organic material, a printed circuit board, glass, quartz, and ceramic.

12. The integrated circuit package recited in claim 10 wherein, in forming the at least one multi-level inductive element, the upper conductive segments and the lower conductive segments are arranged in a stepped manner.

13. The integrated circuit package recited in claim 10 wherein, in forming the at least one multi-level inductive element, the upper conductive segments and the lower conductive segments are arranged in an undulating manner.

14. The integrated circuit package recited in claim 10 wherein, in forming the at least one multi-level inductive element, the upper conductive segments in one row are offset 180 degrees from the upper conductive segments in an adjacent row.

15. An integrated circuit component comprising an inductive element fabricated by:

forming a silicon substrate; and

forming at least one multi-level inductive element on the substrate in a serpentine pattern comprising at least two rows, wherein each row comprises upper conductive segments and lower conductive segments, and in at least one row the upper conductive segments are longer than the lower conductive segments,

wherein, in forming the at least one multi-level inductive element, the at least one multi-level inductive element comprises at least one layer of magnetic material.

16. The integrated circuit component recited in claim 15 wherein, in forming the at least one multi-level inductive element, the upper conductive segments in one row are offset 180 degrees from the upper conductive segments in an adjacent row.

17. An integrated circuit comprising an inductive element fabricated by:

forming at least one multi-level inductive element on a substrate in a serpentine pattern comprising at least two rows, wherein each row comprises upper conductive segments and lower conductive segments, and in at least one row the upper conductive segments are longer than the lower conductive segments,

wherein, in forming, the at least one multi-level inductive element comprises at least one layer of magnetic material.

18. The integrated circuit recited in claim 17 wherein, in forming, the upper conductive segments and the lower conductive segments are arranged in a stepped manner.

19. The integrated circuit recited in claim 17 wherein, in forming, the upper conductive segments and the lower conductive segments are arranged in an undulating manner.

20. The integrated circuit recited in claim 17 wherein, in forming, the upper conductive segments in one row are offset 180 degrees from the upper conductive segments in an adjacent row.