Copper alloy via bottom liner

• US 7,327,033 B2
• Filed: 08/05/2004
• Issued: 02/05/2008
• Est. Priority Date: 08/05/2004
• Status: Expired due to Term

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cooney, Edward C. III, Gambino, Jeffrey P., Edelstein, Daniel C., Stamper, Anthony K., Fitzsimmons, John A.
• Primary Examiner(s): PIZARRO CRESPO, MARCOS D
• Application Number:
  US10/710,828
• Publication Number:
  US 20060027930A1
• Time in Patent Office: 1,279 Days
• Field of Search: 257750-766, 257/E23.141
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76858 by diffusing alloying elements
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 428/12493 Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]

Abstract

Improved mechanical and adhesive strength and resistance to breakage of copper integrated circuit interconnections is obtained by forming a copper alloy in a copper via/wiring connection in an integrated circuit while minimizing adverse electrical effects of the alloy by confining the alloy to an interfacial region of said via/wiring connection and not elsewhere by a barrier which reduces or substantially eliminates the thickness of alloy in the conduction path. The alloy location and composition are further stabilized by reaction of all available alloying material with copper, copper alloys or other metals and their alloys.

Claims

1. An integrated circuit including

a first layer having metal or metal alloy at a surface thereof,

a second layer adjacent to said surface having a metal or metal alloy via therein,

an interlayer connection between metal or metal alloy of said first layer and said metal or metal alloy via comprising a stable alloy region having graded mechanical characteristics, containing a predetermined quantity of alloying material and restricted to an interfacial region of said metal or metal alloy of said first layer and said metal or metal alloy via by a barrier layer,

wherein said metal alloy of said interlayer connection is formed as an annulus in said metal or metal alloy at a surface of said first layer.

2. The integrated circuit as recited in claim 1, wherein said via extends into said metal or metal alloy of said first layer surrounded by said annulus.