Multichip package test

• US 7,327,154 B2
• Filed: 07/27/2005
• Issued: 02/05/2008
• Est. Priority Date: 10/01/2002
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Hyuk, Shim, Hyun-Seop, Lee, Hyoung-Young, Shin, Young-Gu, Heo, Kyoung-Il, Ju, Ki-Bong, Bang, Jeong-Ho
• Primary Examiner(s): KARLSEN, ERNEST F
• Application Number:
  US11/191,494
• Publication Number:
  US 20050258858A1
• Time in Patent Office: 923 Days
• Field of Search: None
• US Class Current: 324/756.05
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls

Abstract

A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Claims

1. A test apparatus, comprising:

a test driver including a drive channel and an input/output channel; and

a test board including a package, the package having mounted thereon a plurality of chips;

where the drive channel connects to a plurality of drive pins, each of the plurality of drive pins associated with a corresponding chip of the plurality of chips in parallel; and

where the input/output channel connects to a plurality of input/output pins, each of the plurality of input/output pins associated with a corresponding chip of the plurality of chips in parallel.

2. The test apparatus of claim 1 where while one of the semiconductor chips is being tested, the drive and input/output pins of other semiconductor chips are configured to be held in a high impedance state.

3. The test apparatus of claim 2 where the semiconductor chips are tested sequentially.

4. The test apparatus of claim 1 where the drive pins includes control and address pins.