Interface circuit

• US 7,327,164 B2
• Filed: 02/07/2006
• Issued: 02/05/2008
• Est. Priority Date: 02/10/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Wang, Jianqin
• Primary Examiner(s): Tran; Anh Q.
• Application Number:
  US11/348,462
• Publication Number:
  US 20060186923A1
• Time in Patent Office: 728 Days
• Field of Search: 326/66, 326/69, 326/73, 326/75, 326/77, 326/126
• US Class Current: 326/77
• CPC Class Codes: H03K 19/001 in bipolar transistor circuits
• CPC Class Codes: H03K 19/01812 with at least one differential stage

Abstract

An interface circuit includes a first and a second input terminal, a first output transistor, a second output transistor, a first output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the first output transistor if the first output transistor is in saturated state and supplies a predetermined current to the control terminal of the first output transistor if the first output transistor is in shutoff state, and a second output controller for implementing control according to a voltage supplied to the first and the second input terminal so that a predetermined current appears at a control terminal of the second output transistor if the second output transistor is in saturated state and supplies a predetermined current to the control terminal of the second output transistor if the second output transistor is in shutoff state.

Claims

1. An interface circuit comprising:

a first input terminal;

a second input terminal;

a first output transistor;

a second output transistor;

a first output controller for implementing control according to a voltage supplied to the first and the second input terminals so that a first predetermined current appears at a control terminal of the first output transistor if the first output transistor is in a saturated state and supplies a second predetermined current to the control terminal of the first output transistor if the first output transistor is in a shutoff state; and

a second output controller for implementing control according to a voltage supplied to the first and the second input terminals so that a third predetermined current appears at a control terminal of the second output transistor if the second output transistor is in a saturated state and supplies a fourth predetermined current to the control terminal of the second output transistor if the second output transistor is in a shutoff state.

2. The interface circuit according to claim 1, comprising:

a first transistor connected to the first input terminal, for outputting a current according to a voltage at the first input terminal;

a first voltage generator for outputting a voltage according to an output of the first transistor;

a second transistor connected to the second input terminal, for outputting a current according to a voltage at the second input terminal; and

a second voltage generator for outputting a voltage according to an output of the second transistor.

3. The interface circuit according to claim 2, wherein the first output controller implements control according to outputs of the first and the second voltage generator so that the first predetermined current appears at a control terminal of the first output transistor if the first transistor is in the saturated state and supplies the second predetermined current to the control terminal of the first output transistor if the first transistor is in the shutoff state.

4. The interface circuit according to claim 2, wherein the second output controller implements control according to outputs of the first and the second voltage generator so that the third predetermined current appears at a control terminal of the second output transistor if the second transistor is in the saturated state and supplies the fourth predetermined current to the control terminal of the second output transistor if the second transistor is in the shutoff state.

5. The interface circuit according to claim 2, wherein the first voltage generator comprises a third transistor for generating a voltage according to a current generated according to an input of the first transistor.

6. The interface circuit according to claim 2, wherein the second voltage generator comprises a fourth transistor for generating a voltage according to a current generated according to an input of the second transistor.

7. The interface circuit according to claim 1, wherein the first and the second output transistors are connected serially between a first power supply and a second power supply or a third power supply.

8. The interface circuit according to claim 1, wherein the first output controller comprises a fifth transistor and a sixth transistor that are connected serially between a first power supply and a second power supply.

9. The interface circuit according to claim 8, wherein the first output controller comprises a seventh transistor and a second current source that are connected serially between the first power supply and a third power supply.

10. The interface circuit according to claim 1, wherein the second output controller comprises a seventh transistor and an eighth transistor that are connected serially between a first power supply and a second power supply.

11. The interface circuit according to claim 1, wherein the first output controller implements control so that the first predetermined current appears at a control terminal of the first output transistor if the first transistor is in the saturated state and supplies the second predetermined current to the control terminal of the first output transistor if the first transistor is in the shutoff state according to outputs of a first transistor connected to the first input terminal and outputting a current according to a voltage at the first input terminal and a first voltage generator for outputting a voltage according to an output of the first transistor, and a second transistor connected to the second input terminal and outputting a current according to a voltage at the second input terminal and a second voltage generator for outputting a voltage according to an output of the second transistor.

12. The interface circuit according to claim 1, wherein the second output controller implements control so that the third predetermined current appears at the control terminal of the second output transistor if the second transistor is in the saturated state and supplies the fourth predetermined current to the control terminal of the second output transistor if the second transistor is in the shutoff state according to outputs of a first transistor connected to the first input terminal and outputting a current according to a voltage at the first input terminal and a first voltage generator for outputting a voltage according to an output of the first transistor, and a second transistor connected to the second input terminal and outputting a current according to a voltage at the second input terminal and a second voltage generator for outputting a voltage according to an output of the second transistor.

13. The interface circuit according to claim 1, wherein said first output transistor and said second output transistor comprise bipolar transistors.

14. The interface circuit according to claim 2, wherein said first transistor and said second transistor comprise bipolar transistors.

15. The interface circuit according to claim 1, wherein a signal input to said control terminal of said first transistor and a signal input to said control terminal of said second transistor are the same in phase, and a signal input to said control terminal of said first transistor and a signal input to said control terminal of said second transistor are different in voltage level.

16. A level conversion circuit, comprising:

a first input bipolar transistor receiving a first input signal;

a second input bipolar transistor receiving a second input signal;

a first output bipolar transistor being driven in phase with said first input bipolar transistor;

a second output bipolar transistor being driven in phase with said second input bipolar transistor; and

a first output controller that provides a stable drive current to a base of said first output bipolar transistor when said first input bipolar transistor is in a shutoff state.

17. The level conversion circuit of claim 16, wherein said first output controller provides a drive current to said first output bipolar transistor so that said first output bipolar transistor smoothly transitions to said shutoff state.

18. The level conversion circuit of claim 17, further comprising:

a second output controller that provides a stable drive current to said second output bipolar transistor when said second input bipolar transistor is in a shutoff state and during transitions to said shutoff state.

19. The level conversion circuit of claim 16, wherein said input signal comprises an Emitter Coupled Logic (ECL) level and an output level of said first and second output bipolar transistors comprises a Complementary Metal Oxide Semiconductor (CMOS ) level.

20. The level conversion circuit of claim 16, wherein said first input bipolar transistor

and said first output bipolar transistor operate from a different power supply.