Low voltage low power class A/B output stage
First Claim
Patent Images
1. A class A/B amplifier output stage comprising:
- a first output driver transistor having a source, a gate, and a drain;
a second output driver transistor having a source, a gate, and a drain, the drain of said first output driver transistor being coupled to the drain of said second output driver transistor;
a first high swing cascode structure coupled to said first output driver transistor and to said second output driver transistor;
a second high swing cascode structure coupled to said first output driver transistor and to said second output driver transistor; and
a voltage source coupled to said first high swing cascode structure, said voltage source providing a minimum operating voltage of about 3VDSsat, where VDSsat is the drain-to-source voltage at saturation for said first output driver transistor and said second output driver transistor, and wherein said first high swing cascode structure and said second high swing cascode structure bias said first output driver transistor to its subthreshold operating region, and bias said second output driver transistor to its subthreshold operating region.
20 Assignments
0 Petitions
Accused Products
Abstract
A CMOS class A/B output stage provides the advantages of high speed operation, low supply voltage requirements, and low quiescent current draw, resulting from the use of subthreshold biasing of the output driver transistors. The architecture of the output stage makes it particularly suitable for use in operational amplifiers in power demanding applications, such as portable instruments, smoke detectors, sensors, or the like.
-
Citations
19 Claims
-
1. A class A/B amplifier output stage comprising:
-
a first output driver transistor having a source, a gate, and a drain; a second output driver transistor having a source, a gate, and a drain, the drain of said first output driver transistor being coupled to the drain of said second output driver transistor; a first high swing cascode structure coupled to said first output driver transistor and to said second output driver transistor; a second high swing cascode structure coupled to said first output driver transistor and to said second output driver transistor; and a voltage source coupled to said first high swing cascode structure, said voltage source providing a minimum operating voltage of about 3VDSsat, where VDSsat is the drain-to-source voltage at saturation for said first output driver transistor and said second output driver transistor, and wherein said first high swing cascode structure and said second high swing cascode structure bias said first output driver transistor to its subthreshold operating region, and bias said second output driver transistor to its subthreshold operating region. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A class A/B amplifier output stage comprising:
-
a PMOS output driver transistor having a source, a gate, and a drain; an NMOS output driver transistor having a source, a gate, and a drain, the drain of said PMOS output driver transistor being coupled to the drain of said NMOS output driver transistor; a first PMOS cascode transistor having a source, a gate, and a drain, the drain of said first PMOS cascode transistor being coupled to the gate of said PMOS output driver transistor; a first NMOS cascode transistor having a source, a gate, and a drain, the drain of said first NMOS cascode transistor being coupled to the gate of said NMOS output driver transistor; a final PMOS cascode transistor having a source, a gate, and a drain, the drain of said final PMOS cascode transistor being coupled to the gate of said NMOS output driver transistor; a final NMOS cascode transistor having a source, a gate, and a drain, the drain of said final NMOS cascode transistor being coupled to the gate of said PMOS output driver transistor; a first PMOS bias transistor having a source, a gate, and a drain, the gate of said first PMOS bias transistor being coupled to the gate of said first PMOS cascode transistor; a first NMOS bias transistor having a source, a gate, and a drain, the gate of said first NMOS bias transistor being coupled to the gate of said first NMOS cascode transistor; a final PMOS bias transistor having a source, a gate, and a drain, the gate of said final PMOS bias transistor being coupled to the gate of said final PMOS cascode transistor, and the drain of said final PMOS bias transistor being coupled to the gate of said first PMOS bias transistor; and a final NMOS bias transistor having a source, a gate, and a drain, the gate of said final NMOS bias transistor being coupled to the gate of said final NMOS cascode transistor, and the drain of said final NMOS bias transistor being coupled to the gate of said first NMOS bias transistor. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
-
-
14. An electronic circuit comprising:
-
a first output driver transistor having a source, a gate, and a drain; a second output driver transistor having a source, a gate, and a drain, the drain of said first output driver transistor being coupled to the drain of said second output driver transistor; a first cascode transistor having a source, a gate, and a drain, the drain of said first cascode transistor being coupled to the gate of said second output driver transistor; a second cascode transistor having a source, a gate, and a drain, the drain of said second cascode transistor being coupled to the gate of said first output driver transistor; a first bias transistor having a source, a gate, and a drain, the gate of said first bias transistor being coupled to the gate of said first cascode transistor; a second bias transistor having a source, a gate, and a drain, the gate of said second bias transistor being coupled to the gate of said second cascode transistor, and the drain of said second bias transistor being coupled to the gate of said first bias transistor; and a differential transistor pair having a common source node coupled to a current source, a first gate node for a first polarity component of an input signal, a second gate node for a second polarity component of said input signal, a first drain node, and a second drain node coupled to the drain of said second bias transistor. - View Dependent Claims (15, 16, 17, 18, 19)
-
Specification