Operation of dual-directional electrostatic discharge protection device

• US 7,327,541 B1
• Filed: 06/22/2004
• Issued: 02/05/2008
• Est. Priority Date: 06/19/1998
• Status: Expired due to Fees

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Deane, Peter, Wang, Albert Z. H., Tsay, Chen H.
• Primary Examiner(s): Hu; Shouxiang
• Application Number:
  US10/873,031
• Time in Patent Office: 1,323 Days
• Field of Search: 438133-140, 438/129, 257/110, 257/112, 257/152, 257/162, 257355-356, 257/173, 257/125, 257/122, 361/51, 361/56
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/87 Thyristor diodes, e.g. Shockley diodes, break-over diodes

Abstract

A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (112, 114, 116, 118, and 120) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors (170 and 180) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.

Claims

1. A method comprising:

providing an electrostatic discharge (ESD) protection structure in an integrated circuit formed from a semiconductor body having a substrate region of a first conductivity type wherein the ESD protection structure comprises (a) a first semiconductor region of a second conductivity type connected to a first terminal, the second conductivity type being opposite to the first conductivity type, (b) a second semiconductor region of the first conductivity type connected to the first terminal and continuous with the first semiconductor region, (c) an electrically floating third semiconductor region of the second conductivity type continuous with the second semiconductor region and separated from the first semiconductor region by the second semiconductor region, (d) a fourth semiconductor region of the first conductivity type connected to a second terminal, continuous with the third semiconductor region, spaced apart from the first semiconductor region, and separated from the second semiconductor region by the third semiconductor region, and (e) a fifth semiconductor region of the second conductivity type connected to the second terminal, continuous with the fourth semiconductor region, spaced apart from the first and second semiconductor regions, and separated from the third semiconductor region by the fourth semiconductor region, the second and fourth semiconductor regions being separated from the substrate region by the third semiconductor region; and

subjecting the integrated circuit to a voltage of magnitude greater than a trigger value such that the voltage is placed across the first and second terminals and such that current dissipating electrical energy associated with the voltage automatically flows through the ESD protection structure when the voltage is placed across the first and second terminals

wherein the third semiconductor region forms, with the second and fourth semiconductor regions, respective pn junctions having respective reverse breakdown voltages whose magnitudes solely determine the trigger value; and

current flows from either terminal through the ESD protection structure to the other terminal substantially only when the voltage across the first and second terminals exceeds the trigger value.

2. A method as in claim 1 wherein the voltage arises from ESD between the first and second terminals.

3. A method as in claim 1 wherein the ESD protection structure enters a snap-back condition when the magnitude of the voltage across the first and second terminals becomes greater than the trigger value.

4. A method as in claim 3 wherein the ESD protection structure exhibits a resistance of 1-2 ohms between the first and second terminals when the ESD protection structure is in the snap-back condition.

5. A method as in claim 1 wherein:

the semiconductor body has a major surface to which the first through fifth semiconductor regions extend;

the second semiconductor region substantially surrounds the first semiconductor region except along the major surface; and

the fourth semiconductor region substantially surrounds the fifth semiconductor region except along the major surface.

6. A method as in claim 5 wherein the third semiconductor region substantially surrounds the second and fourth semiconductor regions except along the major surface.

7. A method as in claim 6 wherein the substrate region substantially surrounds the third semiconductor region except along the major surface.

8. A method as in claim 1 wherein the providing act includes providing each of the second and fourth semiconductor regions as a main portion and a contact portion more heavily doped than the main portion such that the contact portions of the second and fourth semiconductor regions respectively contact the first and second terminals.

9. A method as in claim 8 wherein the voltage arises from ESD between the first and second terminals.

10. A method as in claim 8 wherein the ESD protection structure enters a snap-back condition when the magnitude of the voltage across the first and second terminals becomes greater than the trigger value.

11. A method as in claim 10 wherein the ESD protection structure exhibits a resistance of 1-2 ohms between the first and second terminals when the ESD protection structure is in the snap-back condition.

12. A method as in claim 8 wherein the contact portion of the second semiconductor region is spaced apart from the first semiconductor region, and the contact portion of the fourth semiconductor region is spaced apart from the fifth semiconductor region.

13. A method as in claim 8 wherein:

the semiconductor body has a major surface to which the first through fifth semiconductor regions extend;

the second semiconductor region substantially surrounds the first semiconductor region except along the major surface; and

the fourth semiconductor region substantially surrounds the fifth semiconductor region except along the major surface.

14. A method as in claim 13 wherein:

the main portion of the second semiconductor region also substantially surrounds its contact portion except along the major surface; and

the main portion of the fourth semiconductor region also substantially surrounds its contact portion except along the major surface.

15. A method as in claim 13 wherein the third semiconductor region substantially surrounds the second and fourth semiconductor regions except along the major surface.

16. A method as in claim 15 wherein the substrate region substantially surrounds the third semiconductor region except along the major surface.

17. A method as in claim 8 wherein the first and fifth semiconductor regions are both situated at least partially between the contact portions of the second and fourth semiconductor regions.

18. A method as in claim 8 wherein:

the first semiconductor region is closer to the fifth semiconductor region than to the contact portion of the fourth semiconductor region; and

the fifth semiconductor region is closer to the first semiconductor region than to the contact portion of the second semiconductor region.

19. A method as in claim 18 wherein:

the semiconductor body has a major surface to which the first through fifth semiconductor regions extend;

the first and fifth semiconductor regions and the contact portions of the second and fourth semiconductor regions are shaped generally like rectangles along the major surface; and

the rectangles of the first and fifth semiconductor regions along the major surface are situated at least partially between the rectangles of the contact portions of the second and fourth semiconductor regions along the major surface.

20. A method as in claim 19 wherein:

the rectangles of the first and fifth semiconductor regions along the major surface are largely identical to each other; and

the rectangles of the contact portions of the second and fourth semiconductor regions along the major surface are largely identical to each other.

21. A method as in claim 8 wherein the first and second semiconductor regions and the contact region of the second semiconductor region are in a substantially symmetrical geometrical structure respectively with the fifth and fourth semiconductor regions and the contact region of the fourth semiconductor region along an imaginary line that extends vertically through the third semiconductor region at a location halfway between the second and fourth semiconductor regions.

22. A method as in claim 1 wherein the first and second conductivity types respectively are n-type and p-type.

23. A method as in claim 1 wherein the first and second conductivity types respectively are p-type and n-type.

24. A method as in claim 1 wherein:

the semiconductor body has a major surface to which the first through fifth semiconductor regions extend;

the third semiconductor region substantially surrounds the second and fourth semiconductor regions except along the major surface; and

each of the second and fourth semiconductor regions consists substantially of main semiconductor material and further semiconductor material doped more heavily than the main semiconductor material, substantially surrounded by the main semiconductor material except along the major surface, and having a periphery continuous with the main semiconductor material substantially everywhere except along the major surface.

25. A method as in claim 24 wherein the voltage arises from ESD between the first and second terminals.

26. A method as in claim 24 wherein the ESD protection structure enters a snap-back condition when the magnitude of the voltage across the first and second terminals becomes greater than the trigger value.

27. A method as in claim 26 wherein the ESD protection structure exhibits a resistance of 1-2 ohms between the first and second terminals when the ESD protection structure is in the snap-back condition.

28. A method as in claim 24 wherein the further semiconductor material of the second semiconductor region is spaced apart from the first semiconductor region, and the further semiconductor material of the fourth semiconductor region is spaced apart from the fifth semiconductor region.

29. A method as in claim 24 wherein:

the further semiconductor material of the second semiconductor region consists of a contact portion that contacts the final terminal; and

the further semiconductor material of the fourth semiconductor region consists of a contact portion that contacts the second terminal.

30. A method as in claim 29 wherein the further semiconductor material of the second semiconductor region is spaced apart from the first semiconductor region, and the further semiconductor material of the fourth semiconductor region is spaced apart from the fifth semiconductor region.

31. A method as in claim 24 wherein the first and second semiconductor regions and the further material of the second semiconductor region are in a substantially symmetrical geometrical structure respectively with the fifth and fourth semiconductor regions and the further material of the fourth semiconductor region along an imaginary line that extends vertically through the third semiconductor region at a location halfway between the second and fourth semiconductor regions.

32. A method as in claim 1 wherein:

the semiconductor body has a major surface to which the first through fifth semiconductor regions extend;

the third semiconductor region substantially surrounds the second and fourth semiconductor regions except along the major surface;

each of the second and fourth semiconductor regions consists substantially of main semiconductor material and further semiconductor material doped more heavily than the main semiconductor material;

the further semiconductor material of the second semiconductor region consists of a contact portion that contacts the first terminal; and

the further semiconductor material of the fourth semiconductor region consists of a contact portion that contacts the second terminal.

33. A method as in claim 32 wherein the voltage arises from ESD between the first and second terminals.

34. A method as in claim 32 wherein the ESD protection structure enters a snap-back condition when the magnitude of the voltage across the first and second terminals becomes greater than the trigger value.

35. A method as in claim 34 wherein the ESD protection structure exhibits a resistance of 1-2 ohms between the first and second terminals when the ESD protection structure is in the snap-back condition.

36. A method as in claim 32 wherein the further semiconductor material of the second semiconductor region is spaced apart from the final semiconductor region, and the further semiconductor material of the fourth semiconductor region is spaced apart from the fifth semiconductor region.

37. A method as in claim 32 wherein the first and second semiconductor regions and the further material of the second semiconductor region are in a substantially symmetrical geometrical structure respectively with the fifth and fourth semiconductor regions and the further material of the fourth semiconductor region along an imaginary line that extends vertically through the third semiconductor region at a location halfway between the second and fourth semiconductor regions.

38. A method as in claim 1 wherein the first and second semiconductor regions are in a substantially symmetrical geometrical structure respectively with the fifth and fourth semiconductor regions along an imaginary line that extends vertically through the third semiconductor region at a location halfway between the second and fourth semiconductor regions.

39. A method as in claim 1 wherein the first, second, fourth, and fifth semiconductor regions are spaced apart from the substrate region.

40. A method as in claim 1 wherein the third semiconductor region is continuous with the substrate region.