Communication protocol processor having multiple microprocessor cores connected in series and dynamically reprogrammed during operation via instructions transmitted along the same data paths used to convey communication data

• US 7,328,270 B1
• Filed: 02/25/1999
• Issued: 02/05/2008
• Est. Priority Date: 02/25/1999
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Reents, Daniel B., Craycraft, Donald G., Wakeland, Carl K.
• Primary Examiner(s): Wiley; David
• Assistant Examiner(s): England; David
• Application Number:
  US09/257,521
• Time in Patent Office: 3,267 Days
• Field of Search: 709/200, 709/250, 709220-237, 370/1, 370/401, 370/402, 716/13, 716/14, 712 10- 19, 712221-225, 710/62, 710/65, 710/100, 710/105
• US Class Current: 709/230
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

A communication protocol processor is presented including a transmit unit and a receive unit, each having multiple microprocessor cores connected in series. Each microprocessor core performs an operation upon a stream of communication data, conducted along a data path, according to instructions and associated data stored within a code memory unit. A change in the operation performed by a given microprocessor core is effectuated during communication protocol processor operation by transmitting new instructions and associated data to the microprocessor core along the data path. The new instructions and data modify the existing instructions and associated data stored within the code memory unit. The transmit unit of the communication protocol processor receives packet (i.e., transmit) data in parallel units and produces a framed serial transmit data stream. Each microprocessor core of the transmit unit is assigned one or more tasks which must be accomplished in sequence in order to encapsulate the transmit data stream into frames in accordance with a selected communication protocol. The receive unit receives a framed serial receive data stream and produces packet (i.e., receive) data in parallel units. Each microprocessor core of the receive unit is assigned one or more tasks which must be accomplished in sequence in order to extract receive data from the framed serial receive data stream in accordance with the selected communication protocol. The communication protocol processor may be included within a microcontroller, and the microcontroller employed within a network interface unit (NIU).

Claims

1. A communication protocol processor, comprising:

an interface port; and

a first plurality of microprocessor cores connected in series to receive a serial data stream from said interface port and to perform a protocol processing operation upon said serial data stream;

wherein a first one of said first plurality of microprocessor cores is configured to determine whether a code packet is embedded in said serial data stream and whether said code packet designates said first one of said first plurality of processor cores, to perform a first part of said protocol processing operation upon said serial data stream, and to transmit a resultant serial data stream of said first part to a second one of said first plurality of microprocessor cores;

wherein said second one of said first plurality of microprocessor cores is configured to perform a second part of said protocol processing operation upon said resultant serial data stream; and

wherein in response to said first one of said first plurality of microprocessor cores determining that said code packet is embedded in said serial data stream and designates said first one of said first plurality of microprocessor cores, said first part of said protocol processing operation is configured dependent upon said code packet without said first one of said first plurality of microprocessor cores forwarding said code packet to a subsequent one of said first plurality of microprocessor cores.

2. The communication protocol processor as recited in claim 1, further comprising a respective code memory unit coupled to each of said first plurality of microprocessor cores, wherein each said respective code memory unit is configured to store a plurality of instructions forwarded within said serial transmit data stream, and wherein each said respective code memory unit is further configured to provide said plurality of instructions to its respective microprocessor core.

3. The communication protocol processor as recited in claim 2, wherein each said respective code memory unit is configured to store a unique set of instructions for configuring each said microprocessor core to perform a different part of said protocol processing operation upon said serial data stream.

4. The communication protocol processor as recited in claim 3, wherein each said respective code memory unit corresponding to one of said first plurality of microprocessor cores is configured by storing a code packet designating said corresponding one of said first plurality of microprocessor cores received during performance of the protocol processing operation upon said serial data stream.

5. The communication protocol processor as recited in claim 1, wherein said interface port is a communication network port, said serial data stream is a serial receive data stream, said resultant serial data stream is a resultant serial receive data stream, and said protocol processing operation is a receive protocol processing operation, said communication protocol processor further comprising:

a bus interface port; and

a second plurality of microprocessor cores connected in series to receive a serial transmit data stream from said bus interface port and to perform a transmit protocol processing operation upon said serial transmit data stream, wherein a first one of said second plurality of microprocessor cores is configured to perform a first part of said transmit protocol processing operation upon said serial transmit data stream and to transmit a resultant serial transmit data stream of said first part directly to a second one of said second plurality of microprocessor cores configured to perform a second part of said transmit protocol processing operation upon said resultant serial transmit data stream.

6. The communication protocol processor as recited in claim 1, wherein said interface port is a bus interface port, said serial data stream is a serial transmit data stream, said resultant serial data stream is a resultant serial transmit data stream, and said protocol processing operation is a transmit protocol processing operation, said communication protocol processor further comprising:

a communication network port; and

a second plurality of microprocessor cores connected in series to receive a serial receive data stream from said communication network port and to perform a receive protocol processing operation upon said serial receive data stream, wherein a first one of said second plurality of microprocessor cores is configured to perform a first part of said receive protocol processing operation upon said serial receive data stream and to transmit a resultant serial receive data stream of said first part directly to a second one of said second plurality of microprocessor cores configured to perform a second part of said receive protocol processing operation upon said resultant serial receive data stream.

7. The communication protocol processor as recited in claim 6, wherein said first plurality of microprocessor cores are configured to work together to encapsulate the serial transmit data stream into frames in accordance with a selected communication protocol.

8. The communication protocol processor as recited in claim 6, wherein said second plurality of microprocessor cores are configured to work together to extract communication data from the serial receive data stream in accordance with a selected communication protocol.

9. The communication protocol processor as recited in claim 6, wherein said first and second pluralities of microprocessor cores are coupled in parallel between said bus interface port and said communication network port, and wherein said bus port is adapted for coupling to a bus and said communication network port is adapted for coupling to a transmission medium over which communication data is sent across a communication network.

10. The communication protocol processor as recited in claim 9, wherein said first plurality of microprocessor cores includes an upstream transmit microprocessor core and a downstream transmit microprocessor core, and wherein the remainder of said first plurality of microprocessor cores are connected in series between said upstream transmit microprocessor core and said downstream transmit microprocessor core, and wherein said upstream transmit microprocessor core is coupled to receive said serial transmit data stream, and wherein said downstream transmit microprocessor core is coupled to said communication network port, and wherein said downstream transmit microprocessor core produces a framed serial transmit data stream in accordance with a selected communication protocol and provides said framed serial transmit data stream to said communication network port.

11. The communication protocol processor as recited in claim 9, wherein said second plurality of microprocessor cores includes an upstream receive microprocessor core and a downstream receive microprocessor core, wherein the remainder of said second plurality of microprocessor cores are connected in series between said upstream receive microprocessor core and said downstream receive microprocessor core, and wherein said upstream receive microprocessor core is coupled to receive said serial receive data stream from said communication network port, and wherein said downstream receive microprocessor core produces a serial stream of communication data in accordance with a selected communication protocol.

12. A communication protocol processor, comprising:

an interface port; and

a first plurality of microprocessor cores coupled to receive a serial data stream from said interface port and to perform a protocol processing operation upon said serial data stream, wherein at least one of said first plurality of microprocessor cores is configured by code packets embedded within said serial data stream to perform at least part of said protocol processing operation.

13. The communication protocol processor as recited in claim 12, further comprising a respective code memory unit coupled to each of the microprocessor cores configured by said code packets, wherein each said respective code memory unit is configured to store a plurality of instructions from said code packets, and wherein each said respective code memory unit is further configured to provide said plurality of instructions to its respective microprocessor core.

14. The communication protocol processor as recited in claim 13, wherein each said respective code memory unit is configured to store a unique set of instructions for configuring each said respective microprocessor core to perform a different part of said protocol processing operation upon said serial data stream.

15. The communication protocol processor as recited in claim 13, wherein each said respective code memory unit is configured by storing a code packet received during performance of the protocol processing operation upon said serial data stream.

16. The communication protocol processor as recited in claim 12, wherein said interface port is a communication network port, said serial data stream is a serial receive data stream, and said protocol processing operation is a receive protocol processing operation, said communication protocol processor further comprising:

a bus interface port; and

a second plurality of microprocessor cores coupled to receive a serial transmit data stream from said bus interface port and to perform a transmit protocol processing operation upon said serial transmit data stream, wherein at least one of said second plurality of microprocessor cores is configured by code packets embedded within said serial transmit data stream to perform at least part of said transmit protocol processing operation.

17. The communication protocol processor as recited in claim 12, wherein said interface port is a bus interface port, said serial data stream is a serial transmit data stream, and said protocol processing operation is a transmit protocol processing operation, said communication protocol processor further comprising:

a communication network port; and

a second plurality of microprocessor cores coupled to receive a serial receive data stream from said communication network port and to perform a receive protocol processing operation upon said serial receive data stream, wherein at least one of said second plurality of microprocessor cores is configured by code packets embedded within said serial receive data stream to perform at least part of said receive protocol processing operation.

18. The communication protocol processor as recited in claim 17, wherein said first plurality of microprocessor cores are configured to work together to encapsulate the serial transmit data stream into frames in accordance with a selected communication protocol.

19. The communication protocol processor as recited in claim 17, wherein said second plurality of microprocessor cores are configured to work together to extract communication data from the serial receive data stream in accordance with a selected communication protocol.

20. The communication protocol processor as recited in claim 17, wherein said first and second pluralities of microprocessor cores are coupled in parallel between said bus interface port and said communication network port, and wherein said bus port is adapted for coupling to a bus and said communication network port is adapted for coupling to a transmission medium over which communication data is sent across a communication network.

21. The communication protocol processor as recited in claim 20, wherein said first plurality of microprocessor cores includes an upstream transmit microprocessor core and a downstream transmit microprocessor core, and wherein the remainder of said first plurality of microprocessor cores are connected in series between said upstream transmit microprocessor core and said downstream transmit microprocessor core, and wherein said upstream transmit microprocessor core is coupled to receive said serial transmit data stream, and wherein said downstream transmit microprocessor core is coupled to said communication network port, and wherein said downstream transmit microprocessor core produces a framed serial transmit data stream in accordance with a selected communication protocol and provides said framed serial transmit data stream to said communication network port.

22. The communication protocol processor as recited in claim 20, wherein said second plurality of microprocessor cores includes an upstream receive microprocessor core and a downstream receive microprocessor core, wherein the remainder of said second plurality of microprocessor cores are connected in series between said upstream receive microprocessor core and said downstream receive microprocessor core, and wherein said upstream receive microprocessor core is coupled to receive said serial receive data stream from said communication network port, and wherein said downstream receive microprocessor core produces a serial stream of communication data in accordance with a selected communication protocol.

23. A network interface unit, comprising:

a memory device for storing instructions and transmit data;

a communication protocol processor coupled to said memory device, comprising a first plurality of microprocessor cores coupled to receive a serial transmit data stream and to perform a transmit protocol processing operation upon said serial transmit data stream, wherein at least one of said first plurality of microprocessor cores is configured by code packets embedded within said serial transmit data stream to perform at least part of said transmit protocol processing operation; and

a medium attachment unit adapted for coupling to a network transmission medium of a communication network during use, wherein the medium attachment unit is coupled to said communication protocol processor, and wherein the medium attachment unit is configured to receive the framed serial transmit data stream from said communication protocol processor and to transmit the framed serial transmit data stream upon said network transmission medium.

24. The network interface unit as recited in claim 23, wherein said communication protocol processor further comprises a second plurality of microprocessor cores coupled to receive a serial receive data stream and to perform a receive protocol processing operation upon said serial receive data stream, wherein at least one of said second plurality of microprocessor cores is configured by code packets embedded within said serial receive data stream to perform at least part of said receive protocol processing operation, and wherein said medium attachment unit is further configured to receive the serial receive data stream from the network transmission medium and to provide the serial receive data stream to the communication protocol processor.

25. The network interface unit as recited in claim 24, wherein said second plurality of microprocessor cores produce said serial stream of receive data in accordance with a selected communication protocol.

26. The network interface unit as recited in claim 23, wherein said first plurality of microprocessor cores produce said framed transmit serial data stream in accordance with a selected communication protocol.

27. The network interface unit as recited in claim 23, wherein said communication protocol processor further comprises a respective code memory unit coupled to each of the microprocessor cores configured by said code packets, wherein each said respective code memory unit is configured to store a plurality of instructions from said code packets, wherein each said respective code memory unit is further configured to provide said plurality of instructions to its respective microprocessor core, wherein each said respective code memory unit is configured to store a unique set of instructions for configuring each said respective microprocessor core to perform a different part of said transmit protocol processing operation upon said serial transmit data stream, and wherein each said respective code memory unit is configured by storing a code packet received during performance of the transmit protocol processing upon said serial transmit data stream.

28. A method, comprising:

receiving a serial data stream from an interface port;

performing a protocol processing operation on said serial data stream; and

configuring at least part of said protocol processing operation by embedding code packets within said serial data stream.

29. The method as recited in claim 28, further comprising storing a first plurality of instructions from said code packets in a respective code memory unit coupled to each of a first plurality of microprocessor cores, wherein each said respective code memory unit is configured to store a first unique set of instructions for configuring each said respective microprocessor core to perform a different part of said protocol processing operation upon said serial data stream.

30. The method as recited in claim 29, wherein said code packets are received during said performing a protocol processing operation upon said serial data stream.

31. The method as recited in claim 29, wherein said interface port is a bus interface port, said serial data stream is a serial transmit data stream, said protocol processing operation is a transmit protocol processing operation, and said code packets are transmit code packets, said method further comprising:

receiving a serial receive data stream from an communication network port;

performing a receive protocol processing operation on said serial receive data stream;

configuring at least part of said receive protocol processing operation by embedding receive code packets within said serial receive data stream; and

storing a second plurality of instructions from said receive code packets in a respective code memory unit coupled to each of a second plurality of microprocessor cores, wherein each said respective code memory unit is configured to store a second unique set of instructions for configuring each said respective microprocessor core to perform a different part of said receive protocol processing operation upon said serial receive data stream.

32. A method, comprising:

receiving a serial data stream from an interface port;

performing a first part of a protocol processing operation on said serial data stream in a first one of a first plurality of microprocessor cores;

determining whether a code packet is embedded in said serial data stream and whether said code packet designates a first one of said first plurality of processor cores;

in response to determining that said code packet is embedded in said serial data stream and designates said first one of said first plurality of microprocessor cores, configuring said first part of said protocol processing operation dependent upon said code packet without forwarding said code packet to a subsequent one of said first plurality of microprocessor cores;

transmitting a resultant serial data stream of said first part of said protocol processing operation to a second one of said first plurality of microprocessor cores; and

performing a second part of said protocol processing operation on said resultant serial data stream using said result in said second one of said first plurality of microprocessor cores.

33. The method as recited in claim 32, further comprising storing a first plurality of instructions forwarded within said serial data stream in a respective code memory unit coupled to each of said first plurality of microprocessor cores, wherein each said respective code memory unit is configured to store a first unique set of instructions for configuring each said respective microprocessor core to perform a different part of said protocol processing operation upon said serial data stream.

34. The method as recited in claim 33, further comprising configuring each said respective microprocessor core to perform a different part of said protocol processing operation by storing a code packet designating said respective microprocessor core received during performance of said protocol processing operation upon said serial data stream.

35. The method as recited in claim 33, wherein said interface port is a bus interface port, said serial data stream is a serial transmit data stream, said resultant serial data stream is a resultant serial transmit data stream, and said protocol processing operation is a transmit protocol processing operation, said method further comprising:

receiving a serial receive data stream from an communication network port;

performing a first part of a receive protocol processing operation on said serial receive data stream in a first one of a second plurality of microprocessor cores;

transmitting a resultant serial receive data stream of said first part of said receive protocol processing operation directly to a second one of said second plurality of microprocessor cores;

performing a second part of said receive protocol processing operation on said resultant serial receive data stream using said result in said second one of said second plurality of microprocessor cores; and

storing a first plurality of instructions forwarded within said serial receive data stream in a respective code memory unit coupled to each of said second plurality of microprocessor cores, wherein each said respective code memory unit is configured to store a second unique set of instructions for configuring each said respective microprocessor core to perform a different part of said receive protocol processing operation upon said serial receive data stream.