Method and system for keeping two independent busses coherent
First Claim
1. A method for keeping two independent busses coherent comprising:
- writing data from an Input/Output (I/O) controller to a memory, the I/O controller sending the data to the memory via a first bus connected to a first port of a memory controller and the I/O controller;
sending a tag, from the I/O controller, after the data via the first bus through the first port, the tag being received by the memory controller;
requesting completion status of the data write from the I/O controller by a processing unit, the request being sent to the I/O controller via a second bus connected to a second port of the memory controller and the I/O controller; and
waiting for a tag acknowledgment, by the I/O controller, from the memory controller before providing notification to the processing unit that the data write has completed, wherein the first bus and the second bus are coherent.
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Abstract
Methods and systems for keeping two independent busses coherent that includes writing data from an Input/Output (I/O) controller to a memory. The I/O controller sends the data to the memory via a first bus connected between a first port of a memory controller and the I/O controller. A tag is sent from the I/O controller, after the data, via the first bus through the first port. The tag is received by the memory controller. Completion status of the data write is requested from the I/O controller by a processing unit. The request is sent to the I/O controller via a second bus connected between a second port of the memory controller and the I/O controller. The I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit that the data write has completed. Therefore, the first bus and the second bus are coherent.
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Citations
24 Claims
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1. A method for keeping two independent busses coherent comprising:
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writing data from an Input/Output (I/O) controller to a memory, the I/O controller sending the data to the memory via a first bus connected to a first port of a memory controller and the I/O controller;
sending a tag, from the I/O controller, after the data via the first bus through the first port, the tag being received by the memory controller;
requesting completion status of the data write from the I/O controller by a processing unit, the request being sent to the I/O controller via a second bus connected to a second port of the memory controller and the I/O controller; and
waiting for a tag acknowledgment, by the I/O controller, from the memory controller before providing notification to the processing unit that the data write has completed, wherein the first bus and the second bus are coherent. - View Dependent Claims (2, 3, 4)
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5. A system for keeping two independent busses coherent comprising:
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at least one memory device;
a memory controller operably connected to the at least one memory device;
a processing unit operably connected to the memory controller; and
an Input/Output (I/O) controller operably connected to the memory controller by a first bus and a second bus, the I/O controller writing data to the at least one memory device via the first bus and the memory controller, the I/O controller sending a tag after the memory write to the memory controller via the first bus, the processing unit requesting status from the I/O controller via the memory controller and the second bus, wherein the I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit via the second bus that the data write has completed ensuring that the first bus and the second bus are coherent. - View Dependent Claims (6)
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7. A system for keeping two independent busses coherent comprising:
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at least one memory device;
a memory controller operably connected to the at least one memory device;
at least one processing unit operably connected to the memory controller;
at least one Input/Output (I/O) controller;
at least one first bus, one associated at least one first bus operably connected between one at least one I/O controller and the memory controller;
a second bus operably connected between the memory controller and each at least one I/O controller, each at least one I/O controller writing data to the at least one memory device via the associated at least one first bus and the memory controller, each at least one I/O controller sending a tag after the memory write to the memory controller via the associated first bus, the processing unit requesting status from each at least one I/O controller that initiates the write via the memory controller and the second bus, wherein each at least one I/O controller waits for a tag acknowledgment from the memory controller before providing notification to the processing unit via the second bus that the data write has completed ensuring that each at least one first bus and the second bus are coherent. - View Dependent Claims (8)
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9. A method of an I/O controller comprising
transferring data to a memory controller via a first bus; -
receiving a notification from the memory controller via the first bus after transferring the data to the memory controller; and
providing a processor with a completion status via a second bus that is different than the first bus after receiving the notification from the memory controller. - View Dependent Claims (10, 11, 12, 13, 14)
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15. An I/O controller comprising
a first bus interface for a first bus, a second bus interface for a second bus separate from the first bus, and a direct memory access (DMA) controller to receive via the first bus interface configuration information for a data write, to write data to a memory via the second bus interface based upon the configuration information for the data write, to send, after the data via the second bus interface, a fence that requests a notification of receipt of the fence, and to generate a completion status for the data write based upon the notification.
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18. An apparatus comprising
a processor bus interface to receive configuration information for a data write from a processor bus, a first I/O controller interface to transfer the configuration information for the data write to a first I/O controller bus, a second I/O controller interface to receive data and a fence for the data write from a second I/O controller bus, and a controller to write the data to a memory and to send a notification via the second I/O controller interface in response to the fence.
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21. A system comprising
a processor a memory controller coupled to the processor via a processor bus and adapted to write data to a memory, and an I/O controller coupled to the memory controller via a first I/O controller bus and a second I/O controller bus, wherein the I/O controller receives configuration information for a data write from the processor via the processor bus and the first I/O controller bus, transfers, based upon the configuration information, data and a fence to the memory controller via the second I/O controller bus, and generates a completion status for the based upon a notification received from the memory controller via the second I/O controller bus.
Specification