Interface for a block addressable mass storage system
First Claim
Patent Images
1. A system, comprising:
- a processor;
a nonvolatile mass storage device; and
a host control interface to couple the processor to the nonvolatile mass storage device and issue read/write commands to manage polarity.
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Abstract
A host controller interface to manage the complexity of accessing mass storage that takes into account the special handling needs of various memory technologies such as polymer memories.
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Citations
32 Claims
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1. A system, comprising:
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a processor; a nonvolatile mass storage device; and a host control interface to couple the processor to the nonvolatile mass storage device and issue read/write commands to manage polarity. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system comprising:
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a processor; addressable mass storage devices; and a host controller interface to couple processor commands to the addressable mass storage devices and issue read/write commands to manage polarity. - View Dependent Claims (10, 11)
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12. A system comprising:
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a processor having a transceiver coupled to dual antennas; and a memory module coupled to the processor that is a bus master device having a list of commands to asynchronously process, the memory module including, (a) a memory controller, (b) storage devices to form a mass storage that is coupled to the memory controller, and (c) a host controller coupled to the processor to provide a refresh cycle issued through an interface to the storage devices. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A method including functions in a host control interface to facilitate read/write operations in a mass storage to include at least one of:
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(a) providing a continuous associated command to allow a group of commands to be issued together, (b) using a polarity map to determine how polarity is to handled for a specific access to the mass storage, (c) using a timing control to specify on a per operation basis what timings should be used for read/write operations, (d) using dynamic addressing to write data to a location in a different segment from where the data was read, (e) issuing a multi-command to allow different operations to multiple storage devices in the mass storage, (f) providing a refresh cycle, (g) recording a number or corrections applied to the mass storage, and (h) using a scatter gather list to correctly access data in the mass storage. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A method of error reporting, comprising:
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providing a periodic memory refresh cycle for storage devices; and allowing a memory controller to detect an error and interrupt the software controlling the storage devices to report a memory refresh failure. - View Dependent Claims (25, 26)
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27. An article comprising a machine-readable storage medium containing instructions that if executed enable a host controller interface to control read/write operations for mass storage that include at least one of:
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providing a continuous list of commands to allow a group of commands to be issued together; using a polarity map to determine how polarity is to be handled for a specific access of the mass storage; using a timing control to specify on a per operation basis what timing should be used for read/write operations; using dynamic addressing to write data to a location in a different segment of the mass storage from where the data was read; issuing a multi-command to allow different operations to multiple devices in the mass storage; providing a refresh cycle; and reporting a number of memory error corrections. - View Dependent Claims (28, 29, 30, 31, 32)
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Specification