Interface for a block addressable mass storage system

• US 7,328,304 B2
• Filed: 02/27/2004
• Issued: 02/05/2008
• Est. Priority Date: 02/27/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Garney, John I., Faber, Robert W., Royer, Robert J. Jr.
• Primary Examiner(s): Bragdon; Reginald
• Assistant Examiner(s): Namazi; Mehdi
• Application Number:
  US10/788,717
• Publication Number:
  US 20050193164A1
• Time in Patent Office: 1,439 Days
• Field of Search: None
• US Class Current: 711/113
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/068 Hybrid storage device
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A host controller interface to manage the complexity of accessing mass storage that takes into account the special handling needs of various memory technologies such as polymer memories.

Claims

1. A system, comprising:

a processor;

a nonvolatile mass storage device; and

a host control interface to couple the processor to the nonvolatile mass storage device and issue read/write commands to manage polarity.

2. The system of claim 1 wherein the nonvolatile mass storage device is a disk cache.

3. The system of claim 1 wherein the nonvolatile mass storage device has polymer memory devices.

4. The system of claim 3 wherein the nonvolatile mass storage device having polymer memory devices is a disk cache.

5. The system of claim 1 wherein polarity management ensures that data is stored in the nonvolatile mass storage device with a polarity opposite of that last used for a memory word.

6. The system of claim 1 wherein polarity management includes an explicit polarity control with a polarity indicator to determine data polarity for each write.

7. The system of claim 1 wherein polarity management includes a recovered polarity that uses a last polarity from a read operation for a subsequent write operation.

8. The system of claim 1 wherein polarity management includes an automatic polarity where contents of a polarity map determine polarity on reads and polarity in the polarity map is toggled for writes.

9. A system comprising:

a processor;

addressable mass storage devices; and

a host controller interface to couple processor commands to the addressable mass storage devices and issue read/write commands to manage polarity.

10. The system of claim 9 wherein a host controller detects an error and reports a number of error corrections.

11. The system of claim 9 wherein a polarity map is used to determine how polarity is to be handled for a specific access.

12. A system comprising:

a processor having a transceiver coupled to dual antennas; and

a memory module coupled to the processor that is a bus master device having a list of commands to asynchronously process, the memory module including,

(a) a memory controller,

(b) storage devices to form a mass storage that is coupled to the memory controller, and

(c) a host controller coupled to the processor to provide a refresh cycle issued through an interface to the storage devices.

13. The system of claim 12 wherein the storage devices are polymer memory devices.

14. The system of claim 12 wherein the storage devices are flash memory devices.

15. The system of claim 12 wherein the list of commands are processed without involvement by the processor.

16. The system of claim 12 wherein data stored by the storage devices on the memory module is not directly accessible by processor instructions.

17. The system of claim 16 wherein the data stored by the storage devices on the memory module is copied to/from system memory.

18. A method including functions in a host control interface to facilitate read/write operations in a mass storage to include at least one of:

(a) providing a continuous associated command to allow a group of commands to be issued together,

(b) using a polarity map to determine how polarity is to handled for a specific access to the mass storage,

(c) using a timing control to specify on a per operation basis what timings should be used for read/write operations,

(d) using dynamic addressing to write data to a location in a different segment from where the data was read,

(e) issuing a multi-command to allow different operations to multiple storage devices in the mass storage,

(f) providing a refresh cycle,

(g) recording a number or corrections applied to the mass storage, and

(h) using a scatter gather list to correctly access data in the mass storage.

19. The method of claim 18, wherein facilitating read\write operations in the mass storage includes using the mass storage having a ferroelectric polarizable material.

20. The method of claim 18, wherein facilitating read\write operations in the mass storage includes using the mass storage having a resistive change polymer memory.

21. The method of claim 18, wherein facilitating read\write operations in the mass storage further includes facilitating read\write operations in a polymer storage.

22. The method of claim 18, wherein facilitating read\write operations in the mass storage further includes facilitating read\write operations in a disk cache.

23. The method of claim 22 further includes storing a minimum and maximum cache line size and metadata size in the disk cache.

24. A method of error reporting, comprising:

providing a periodic memory refresh cycle for storage devices; and

allowing a memory controller to detect an error and interrupt the software controlling the storage devices to report a memory refresh failure.

25. The method of claim 24 further including:

incorporating Polymer Ferroelectric Memory (PFEM) devices for the storage devices.

26. The method of claim 24 wherein providing the periodic memory refresh cycle for storage devices further includes providing the periodic memory refresh cycle for cache storage devices.

27. An article comprising a machine-readable storage medium containing instructions that if executed enable a host controller interface to control read/write operations for mass storage that include at least one of:

providing a continuous list of commands to allow a group of commands to be issued together;

using a polarity map to determine how polarity is to be handled for a specific access of the mass storage;

using a timing control to specify on a per operation basis what timing should be used for read/write operations;

using dynamic addressing to write data to a location in a different segment of the mass storage from where the data was read;

issuing a multi-command to allow different operations to multiple devices in the mass storage;

providing a refresh cycle; and

reporting a number of memory error corrections.

28. The article of claim 27 wherein the mass storage is a flash memory.

29. The article of claim 27 wherein the mass storage is a polymer storage.

30. The article of claim 29 wherein the polymer storage includes a ferroelectric polarizable material.

31. The article of claim 29 wherein the polymer storage includes a resistive change polymer memory.

32. The article of claim 29 wherein the mass storage is a disk cache.