System and method for managing mirrored memory transactions and error recovery
First Claim
Patent Images
1. In a data processing system having a memory control device including at least two mirrored memory ports, a system for processing read requests comprising:
- a memory controller that generates and processes signals for reading and writing data from and to a system memory that employs memory mirroring in which a first set of memory modules is mirrored by a corresponding second set of memory modules, said memory controller including a memory access control module that controls reading and writing between said memory controller and said first and second set of memory modules, said memory access control module receiving read and write requests on a system interconnect;
a memory bus comprising a pair of memory ports that communicatively couple said memory controller with said first and second set of memory modules;
said memory controller further including a pair of port interface modules for respectively interfacing each of said pair of memory ports with said memory access control module, each of said pair of port interface modules comprising;
a write request buffer for storing pending write requests received by said memory access control module;
a read request buffer for storing pending read requests received by said memory access control module;
a command generator module including arbitration logic for selecting a read or write request to be issued onto said memory bus from among a plurality of pending read and write requests stored within said read and write request buffers; and
a conflict queue module that, in response to read and write requests being issued onto said memory bus, holds the issued read and write requests pending processing of the issued read and write requests;
a central data buffer coupled to said memory bus, said central data buffer storing data for pending read and write requests issued onto said memory bus;
an error detection module coupled to said central data buffer, said error detection module containing logic for detecting uncorrectable errors in data returned by execution of read requests;
wherein said memory access control module includes a read scheduler module that issues read requests only to a specified one of said pair of memory ports; and
wherein said conflict queue module includes logic for, responsive to receiving an uncorrectable error signal from said error detection module indicating an uncorrectable error resulting from a read request issued to the specified memory port, issuing the read request to the other of the pair of memory ports prior to reporting a read request status to said read request buffer and holding the corresponding read request during said issuing of the read request to the other of the pair of memory ports prior to said reporting the read request status to said read request buffer.
3 Assignments
0 Petitions
Accused Products
Abstract
In a data processing system having a memory control device including at least two mirrored memory ports, a method, system, and article of manufacture for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.
26 Citations
9 Claims
-
1. In a data processing system having a memory control device including at least two mirrored memory ports, a system for processing read requests comprising:
-
a memory controller that generates and processes signals for reading and writing data from and to a system memory that employs memory mirroring in which a first set of memory modules is mirrored by a corresponding second set of memory modules, said memory controller including a memory access control module that controls reading and writing between said memory controller and said first and second set of memory modules, said memory access control module receiving read and write requests on a system interconnect; a memory bus comprising a pair of memory ports that communicatively couple said memory controller with said first and second set of memory modules; said memory controller further including a pair of port interface modules for respectively interfacing each of said pair of memory ports with said memory access control module, each of said pair of port interface modules comprising; a write request buffer for storing pending write requests received by said memory access control module; a read request buffer for storing pending read requests received by said memory access control module; a command generator module including arbitration logic for selecting a read or write request to be issued onto said memory bus from among a plurality of pending read and write requests stored within said read and write request buffers; and a conflict queue module that, in response to read and write requests being issued onto said memory bus, holds the issued read and write requests pending processing of the issued read and write requests; a central data buffer coupled to said memory bus, said central data buffer storing data for pending read and write requests issued onto said memory bus; an error detection module coupled to said central data buffer, said error detection module containing logic for detecting uncorrectable errors in data returned by execution of read requests; wherein said memory access control module includes a read scheduler module that issues read requests only to a specified one of said pair of memory ports; and wherein said conflict queue module includes logic for, responsive to receiving an uncorrectable error signal from said error detection module indicating an uncorrectable error resulting from a read request issued to the specified memory port, issuing the read request to the other of the pair of memory ports prior to reporting a read request status to said read request buffer and holding the corresponding read request during said issuing of the read request to the other of the pair of memory ports prior to said reporting the read request status to said read request buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeLenovo International Limited (Lenovo Group Ltd.)
-
Original AssigneeInternational Business Machines Corporation
-
InventorsHillier, Philip Rogers III, McGlone, Elizabeth A., Kirscht, Joseph Allen
-
Primary Examiner(s)Sparks; Donald
-
Assistant Examiner(s)OTTO, ALAN
-
Application NumberUS11/050,291Publication NumberTime in Patent Office1,097 DaysField of Search711/149, 711/114, 711/155, 711/168, 714/770, 714/6US Class Current711/149CPC Class CodesG06F 11/141 for bus or memory accessesG06F 11/1666 where the redundant compone...G06F 11/20 using active fault-masking,...
