Memory controller and method for optimized read/modify/write performance
First Claim
1. A memory controller comprising:
- a read queue;
a write queue;
wherein the memory controller translates a read-modify-write (RMW) command into a read command on the read queue and a write command on the write queue and controls a sequence of executing the read command and the write command;
a RMW queue to hold the RMW command; and
wherein the memory controller combines a plurality of RMW commands in the RMW queue that modify a same cacheline.
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Abstract
A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.
10 Citations
17 Claims
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1. A memory controller comprising:
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a read queue; a write queue; wherein the memory controller translates a read-modify-write (RMW) command into a read command on the read queue and a write command on the write queue and controls a sequence of executing the read command and the write command; a RMW queue to hold the RMW command; and wherein the memory controller combines a plurality of RMW commands in the RMW queue that modify a same cacheline. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory controller comprising:
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a write queue for write operations to a memory coupled to the memory controller; a read queue for read operations to the memory; a RMW queue for RMW operations to the memory; in response to a RMW command issued to the memory controller, the memory controller performing the steps of; writing a read command portion of the RMW command to the read queue; waiting for data from an executing read command portion of the RMW command; combining data from the read command portion of the RMW command with partial data from the RMW command into a single write command; and writing the single write command to the write queue; and combining entries in the RMW queue that access a same cacheline. - View Dependent Claims (8, 9)
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10. A method for a memory controller to access memory, the method comprising the steps of:
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writing a read command to a read queue; writing a write command to a write queue; translating a RMW command into a read command on the read queue and a write command on the write queue; controlling a sequence of executing the read command and the write command writing a RMW command to a RMW queue; and combining a plurality of RMW commands in the RMW queue that modify a same cacheline. - View Dependent Claims (11, 12, 13, 14)
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15. A method for a memory controller to access memory, the method comprising the steps of:
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writing a read command to a read queue; writing a write command to a write queue; writing a RMW command to a RMW queue; writing a read command portion of the RMW command to the read queue; waiting for data from the executing read command portion of the RMW command; combining the data from the read command portion of the RMW command with partial data from the RMW command into a single write command; writing the single write command to the write queue; and wherein the memory controller further performs the step of combining entries in the RMW queue that access a same cacheline. - View Dependent Claims (16, 17)
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Specification