Error correction for programmable logic integrated circuits

• US 7,328,377 B1
• Filed: 01/27/2004
• Issued: 02/05/2008
• Est. Priority Date: 01/27/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Lewis, David, Betz, Vaughn
• Primary Examiner(s): Chu; Gabriel
• Assistant Examiner(s): BONURA, TIMOTHY M
• Application Number:
  US10/766,464
• Time in Patent Office: 1,470 Days
• Field of Search: 714/48, 714/52, 714/54
• US Class Current: 714/48
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing

Abstract

Systems and methods for detecting and correcting errors in programmable logic ICs are provided. In one embodiment, a scrubber periodically reads the memory cells in a programmable logic IC, detects and corrects any errors, and writes the corrected contents back into the memory cell. In another embodiment, regions of memory cells in a programmable logic IC each have associated error correcting circuitry which operates to continuously detect and correct errors as they occur. Error correcting circuitry can further be designed to reduce static hazards. It may be more desirable to design programmable logic IC routing architectures that reduce the number of memory cells needed to implement a given function. Error correcting circuitry can be provided for configuration memory or for an embedded memory block on a programmable logic IC.

Claims

1. A circuit that corrects errors in configuration data stored on a programmable logic device, the circuit comprising:

a memory, incorporated in the programmable logic device, in which the configuration data and error check data associated with the configuration data are stored; and

error correction circuitry coupled to at least some of the memory to analyze the configuration data stored in the memory to determine if any values have changed after initial configuration of the memory and to correct any values that have changed;

wherein;

the configuration data are stored in an array including representative rows and representative columns of cells, each cell storing one bit of the configuration data; and

the error check data are stored in a last additional representative column of cells and a last additional representative row of cells in the array, each cell storing one bit of the error check data.

2. The circuit of claim 1 wherein the error correction circuitry comprises at least one scrubbing circuit operative to:

read from the memory a portion of the configuration data and an associated portion of the error check data; and

apply an error correcting code on the portion of the configuration data and the associated portion of the error check data to determine whether at least one bit in the portion of the configuration data has an error and to correct the at least one bit that has the error.

3. The circuit of claim 2 wherein the scrubbing circuit is associated with a subset of the configuration data and an associated subset of the error check data.

4. The circuit of claim 1 wherein the error correction circuitry comprises:

first circuitry having an input operative to receive data from each cell in a representative row of the array and an output, the first circuitry generating a first parity for the data in the representative row at the output;

second circuitry having an input operative to receive data from each cell in a representative column of the array and an output, the second circuitry generating a second parity for the data in the representative column at the output;

third circuitry having a first input operative to receive the output of the first circuitry, having a second input operative to receive the output of the second circuitry, and an output, the third circuitry sending a signal at the output indicative of whether an error has occurred in a cell in the representative row and the representative column based on the first parity and the second parity; and

fourth circuitry having a first input operative to receive the output of the third circuitry, a second input operative to receive data from the cell in the representative row and the representative column, and an output, the fourth circuitry sending a signal at the output having a correct value.

5. The circuit of claim 4 wherein the correct value is:

the data from the cell when the output of the first logic gate indicates that no error has occurred; and

the complement of the data from the cell when the output of the first logic gate indicates that the error has occurred.

6. The circuit of claim 4 further comprising fifth circuitry operative to write the correct value into the cell.

7. The circuit of claim 1 wherein the error correction circuitry comprises:

first circuitry having an input operative to receive data from all but one cell in a representative row of the array and an output, the first circuitry generating a first parity for the data from all but the one cell in the representative row at the output;

second circuitry having an input operative to receive data from all but the one cell in a representative column of the array and an output, the second circuitry generating a second parity for the data from all but the one cell in the representative column at the output; and

third circuitry having a first input operative to receive the output of the first circuitry, a second input operative to receive the output of the second circuitry, a third input operative to receive data from the one cell, and an output, the third circuitry generating a correct value at the output.

8. The circuit of claim 7 further comprising fourth circuitry operative to write the correct value into the one cell.

15. A digital processing system comprising:

processing circuitry;

a memory coupled to the processing circuitry; and

a programmable logic device as defined in claim 1 coupled to the processing circuitry and the memory.

16. A printed circuit board on which is mounted a programmable logic device as defined in claim 15.

17. The printed circuit board defined in claim 16 further comprising:

a memory mounted on the printed circuit board and coupled to the programmable logic device.

18. The printed circuit board defined in claim 16 further comprising:

processing circuitry mounted on the printed circuit board and coupled to the programmable logic device.

9. A circuit that corrects errors in configuration data stored on a programmable logic device, the circuit comprising:

a memory, incorporated in the programmable logic device, in which the configuration data and error check data associated with the configuration data are stored; and

error correction circuitry coupled to at least some of the memory to analyze the configuration data stored in the memory to determine if any values have changed after initial configuration of the memory and to correct any values that have changed;

wherein;

each bit of the configuration data is stored in a first cell, a second cell, and a third cell in the memory.

10. The circuit of claim 9 wherein the error correction circuitry generates as output a same bit value that is stored in at least two of the first cell, the second cell, and the third cell.

11. The circuit of claim 10 wherein the error correction circuitry comprises circuitry having a first input operative to receive a bit from the first cell, a second input operative to receive a bit from the second cell, a third input operative to receive a bit from the third cell, and an output, the circuitry generating a correct bit value at the output.

12. The circuit of claim 11 further comprising second circuitry operative to write the correct bit value into at least one of the first cell, the second cell, and the third cell.

13. A circuit that corrects errors in configuration data stored on a programmable logic device, the circuit comprising:

a memory, incorporated in the programmable logic device, in which the configuration data and error check data associated with the configuration data are stored;

error correction circuitry coupled to at least some of the memory to analyze the configuration data stored in the memory to determine if any values have changed after initial configuration of the memory and to correct any values that have changed;

a resistive element coupled to an output of the error correction circuitry; and

a capacitive load coupled to the resistive element, wherein the resistive element and the capacitive load are operative to reduce static hazards associated with the error correction circuitry.

14. The circuit of claim 13 wherein the resistive element is one of a polysilicon wire, a current starved pass gate, and a current starved inverter.

19. A circuit that corrects errors in configuration data stored on a programmable logic device comprising:

a memory array of representative rows and representative columns of cells in which the configuration data and error check data associated with the configuration data are stored;

first circuitry having an input operative to receive data from each cell in a representative row of the array and an output, the first circuitry generating a first parity for the data in the representative row at the output;

second circuitry having an input operative to receive data from each cell in a representative column of the array and an output, the second circuitry generating a second parity for the data in the representative column at the output;

third circuitry having a first input operative to receive the output of the first circuitry, having a second input operative to receive the output of the second circuitry, and an output, the third circuitry sending a signal at the output indicative of whether an error has occurred in a cell in the representative row and the representative column based on the first parity and the second parity; and

fourth circuitry having a first input operative to receive the output of the third circuitry, a second input operative to receive data from the cell in the representative row and the representative column, and an output, the fourth circuitry sending a signal at the output having a correct value.

20. The circuit of claim 19 wherein the correct value is:

the data from the cell when the output of the first logic gate indicates that no error has occurred; and

the complement of the data from the cell when the output of the first logic gate indicates that an error has occurred.

21. The circuit of claim 19 further comprising fifth circuitry operative to write the correct value into the cell.

22. A circuit that corrects errors in configuration data stored on a programmable logic device comprising:

a memory array of representative rows and representative columns of cells in which the configuration data and error check data associated with the configuration data are stored;

first circuitry having an input operative to receive data from all but one cell in a representative row of the array and an output, the first circuitry generating a first parity for the data from all but the one cell in the representative row at the output;

second circuitry having an input operative to receive data from all but the one cell in a representative column of the array and an output, the second circuitry generating a second parity for the data from all but the one cell in the representative column at the output; and

third circuitry having a first input operative to receive the output of the first circuitry, a second input operative to receive the output of the second circuitry, a third input operative to receive data from the one cell, and an output, the third circuitry generating a correct value at the output.

23. The circuit of claim 22 further comprising fourth circuitry operative to write the correct value into the one cell.

24. A method for correcting errors in configuration data stored on a programmable logic device comprising:

generating error check data associated with the configuration data and storing the error check data in a memory, incorporated in the programmable logic device, in which the configuration data are stored;

reading a portion of the configuration data and an associated portion of the error check data;

determining if an error has occurred based on the portion of the configuration data and the associated portion of the error check data; and

correcting the portion of the configuration data in response to the determining;

wherein;

the portion of the configuration data is at least two partial representative columns of cells in the memory that are physically non-contiguous.

25. The method of claim 24 wherein the portion of the configuration data is at least one representative column of cells in the memory.

26. The method of claim 24 wherein the portion of the configuration data is at least one partial representative column of cells in the memory.

27. The method of claim 24 wherein the portion of the configuration data is at least two partial representative columns of cells in the memory that are physically contiguous.

28. The method of claim 24 wherein the determining comprises applying an error correcting code on the portion of the configuration data and the associated portion of the error check data.

29. The method of claim 28 wherein the error correcting code is one of a Hamming Code, a Reed-Solomon Code, and a Product Code.

30. The method of claim 24 wherein the correcting comprises writing the corrected portion of the configuration data into the memory.