Method and apparatus using device defects as an identifier

• US 7,328,384 B1
• Filed: 09/29/2005
• Issued: 02/05/2008
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lawman, Gary R., Trimberger, Stephen M., Kulkarni, Chidamber R.
• Primary Examiner(s): Kerveros; James C.
• Application Number:
  US11/238,781
• Time in Patent Office: 859 Days
• Field of Search: 714/736, 714/725
• US Class Current: 714/725
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]

Abstract

A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.

Claims

1. A method for providing an identifier for an integrated circuit, comprising;

writing data to memory of the integrated circuit;

wherein the integrated circuit is a field programmable gate array (FPGA) and the writing data to memory of the integrated circuit comprises loading configuration data into configuration memory cells of the FPGA that controls interconnect multiplexors and forms paths through multiple interconnect multiplexors of the FPGA;

identifying defects based upon the writing of the data;

wherein the identifying includes generating a set of bits that identifies cells of the memory that are defective;

the identifying defects based upon the writing of the data further comprises checking signals transmitted on the paths through the multiple interconnect multiplexors and identifying each path failing to transmit a signal;

deriving an identifier for the integrated circuit using the identification of the defects;

wherein the deriving includes generating a value from the set of bits that identifies defective memory cells, wherein the value is represented with fewer bits than the set of bits; and

wherein the deriving an identifier for the FPGA using the identification of the defects comprises generating an identifier for the FPGA using the identification of each path failing to transmit a signal; and

storing the value.

2. The method of claim 1, wherein the storing includes storing the identifier on the integrated circuit.

3. The method of claim 1, wherein the storing includes storing the identifier on a non-volatile memory die stacked on the integrated circuit.

4. The method of claim 1, wherein the generating includes generating an encryption key based on the set of bits that identify the defective memory cells.

5. The method of claim 1, wherein the generating includes encrypting the set of bits that identifies the defective memory cells.

6. The method of claim 1, wherein the generating includes combining the set of bits with a timestamp.

7. An integrated circuit (IC) for providing an identifier based on memory cell defects, comprising:

a field programmable gate array (FPGA);

a configurable array of memory cells, the array comprising a first portion storing user data and a second portion storing error correction code (ECC) data, the array having a read port;

wherein the array of memory cells configures resources of the FPGA;

an ECC generation and correction circuit having a plurality of input terminals coupled to the read port of the array and a first plurality of output terminals; and

a controller, coupled to the configurable array of memory cells, the controller configurable to write data to memory cells of the integrated circuit, to identify defects based upon the data written to the memory cells and to derive an identifier for the integrated circuit using the identification of the defects,

wherein the controller writes data to the memory cells by loading configuration data into configuration memory cells that controls interconnect multiplexors and forms paths through multiple interconnect multiplexors of the FPGA, identifies defects by checking signals transmitted on the paths through the multiple interconnect multiplexors and identifying each path failing to transmit a signal, and derives an identifier for the FPGA using the identification of the defects by generating an identifier for the FPGA using the identification of each path failing to transmit a signal,

wherein the controller is further configurable to generate a set of bits that identifies cells of the memory that are defective, generate a value from the set of bits that identifies defective memory cells, wherein the value is represented with fewer bits than the set of bits, and store the value.

8. The IC of claim 7 further comprising generating an encryption key based on the identifier.

9. A program storage device, comprising:

program instructions executable by a processing device to perform operations for providing an identifier for an integrated circuit, the operations comprising

writing data to memory of the integrated circuit;

wherein the integrated circuit is a field programmable gate array (FPGA);

wherein the writing data to memory of the integrated circuit comprises loading configuration data into configuration memory cells of the FPGA that controls interconnect multiplexors and forms paths through multiple interconnect multiplexors of the FPGA;

identifying defects based upon the writing of the data;

wherein the identifying defects based upon the writing of the data further comprises checking signals transmitted on the paths through the multiple interconnect multiplexors and identifying each path failing to transmit a signal;

wherein the identifying includes generating a set of bits that identifies cells of the memory that are defective;

deriving an identifier for the integrated circuit using the identification of the defects;

wherein the deriving an identifier for the FPGA using the identification of the defects comprises generating an identifier for the FPGA using the identification of each path failing to transmit a signal;

wherein the deriving includes generating a value from the set of bits that identifies defective memory cells, wherein the value is represented with fewer bits than the set of bits; and

storing the value.