Low density parity check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses

• US 7,328,398 B2
• Filed: 05/12/2006
• Issued: 02/05/2008
• Est. Priority Date: 08/15/2002
• Status: Expired due to Term

• Current Assignee: Access To Advanced Health Institute
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): CHASE, SHELLY A
• Application Number:
  US11/433,028
• Publication Number:
  US 20060218465A1
• Time in Patent Office: 634 Days
• Field of Search: 714/807, 714/794, 714/800
• US Class Current: 714/794
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Claims

1. An apparatus, comprising:

a min* functional block, that performs min* processing, that is operable to;

determine a first sign function value using a first value;

determine a second sign function value using a second value; and

update a check node extrinsic information value, that is used in decoding an LDPC (Low Density Parity Check) coded signal, using the first sign function value and the second sign function value.

2. The apparatus of claim 1, wherein:

the min* functional block is operable to;

determine a minimum value from among the first value and the second value;

determine a logarithmic correction factor based on the first value and the second value; and

update the check node extrinsic information value using the first sign function value, the second sign function value, the minimum value and the logarithmic correction factor.

3. The apparatus of claim 1, further comprising:

a memory that stores a plurality of predetermined logarithmic correction factors; and

wherein;

at least one predetermined logarithmic correction factor of the plurality of predetermined logarithmic correction factors is an absolute value of a difference between the first value and the second value.

4. The apparatus of claim 1, further comprising:

a memory that stores a plurality of predetermined logarithmic correction factors; and

wherein;

at least one predetermined logarithmic correction factor of the plurality of predetermined logarithmic correction factors is a function of an absolute value of a difference between the first value and the second value.

5. The apparatus of claim 1, further comprising:

a memory that stores a plurality of predetermined logarithmic correction factors; and

wherein;

the min* functional block is operable to;

determine a minimum value from among the first value and the second value;

select the logarithmic correction factor from the plurality of predetermined logarithmic correction factors stored in the memory based on the first value and the second value; and

update the check node extrinsic information value using the first sign function value, the second sign function value, the minimum value, and the logarithmic correction factor.

6. The apparatus of claim 1, wherein:

the min* functional block is operable to;

multiply the first sign function value by the second sign function value.

7. The apparatus of claim 1, wherein:

the min* functional block is operable to;

determine a minimum value from among the first value and the second value;

determine a logarithmic correction factor based on the first value and the second value;

subtract the logarithmic correction factor from the minimum value thereby generating a min* resultant; and

multiply the first sign function value by the second sign function value and by the min* resultant.

8. The apparatus of claim 1, wherein:

the min* functional block is operable to perform min*+ processing and min*−

processing;

the min*+ processing operates using a plurality of values that correspond, at least in part, to a plurality of variable node extrinsic information values to generate an intermediate variable resultant; and

the min*−

processing operates using the intermediate variable resultant and at least one variable node extrinsic information value of the plurality of variable node extrinsic information values.

9. The apparatus of claim 1, wherein:

the apparatus is a decoder, a receiver, or a transceiver that is implemented within a communication system; and

an LDPC code by which the LDPC coded signal is generated is a regular LDPC code or an irregular LDPC code.

10. An apparatus, comprising:

a min** functional block, that performs min** processing using a plurality of values that correspond, at least in part, to a plurality of variable node extrinsic information values, that is operable to update a check node extrinsic information value, that is used in decoding an LDPC (Low Density Parity Check) coded signal, using the plurality of values.

11. The apparatus of claim 10, wherein:

a first value of the plurality of values corresponds to a first variable node extrinsic information value of the plurality of variable node extrinsic information values; and

a second value of the plurality of values corresponds to a second variable node extrinsic information value of the plurality of variable node extrinsic information values.

12. The apparatus of claim 10, wherein:

the min** functional block is operable to;

determine a first sign function value using a first value of the plurality of values;

determine a second sign function value using a second value of the plurality of values; and

update the check node extrinsic information value, that is used in decoding the LDPC coded signal, using by also using the first value, the second value, the first sign function value, and the second sign function value.

13. The apparatus of claim 10, wherein:

the min** functional block is operable to;

determine a minimum value from among a first value of the plurality of values and a second value of the plurality of values;

determine a logarithmic correction factor based on the first value and the second value; and

update the check node extrinsic information value using the minimum value and the logarithmic correction factor.

14. The apparatus of claim 10, further comprising:

a memory that stores a plurality of predetermined logarithmic correction factors; and

wherein;

at least one predetermined logarithmic correction factor of the plurality of predetermined logarithmic correction factors is a function of at least one of an absolute value of a difference between a first value of the plurality of values and a second value of the plurality of values and a sum of the first value and the second value.

15. The apparatus of claim 10, wherein:

the min** functional block is operable to;

determine a first sign function value using a first value of the plurality of values;

determine a second sign function value using a second value of the plurality of values;

determine a minimum value from among a first value of the plurality of values and a second value of the plurality of values;

determine a logarithmic correction factor based on the first value and the second value;

add the logarithmic correction factor to the minimum value thereby generating a min** resultant; and

multiply the first sign function value by the second sign function value and by the min** resultant.

16. The apparatus of claim 10, wherein:

the min** functional block is operable to perform min**+ processing and min**−

processing;

the min**+ processing operates using the plurality of values to generate an intermediate variable resultant; and

the min**−

processing operates using the intermediate variable resultant and at least one variable node extrinsic information value of the plurality of variable node extrinsic information values.

17. The apparatus of claim 10, wherein:

the apparatus is a decoder, a receiver, or a transceiver that is implemented within a communication system; and

an LDPC code by which the LDPC coded signal is generated is a regular LDPC code or an irregular LDPC code.

19. The apparatus of claim 10, wherein:

the min** functional block is operable to perform min**+ processing and min**−

processing;

the min**+ processing operates using the plurality of values to generate an intermediate variable resultant; and

the min**−

processing operates using the intermediate variable resultant and at least one variable node extrinsic information value of the plurality of variable node extrinsic information values.

20. The apparatus of claim 19, wherein:

the apparatus is a decoder, a receiver, or a transceiver that is implemented within a communication system; and

an LDPC code by which the LDPC coded signal is generated is a regular LDPC code or an irregular LDPC code.

18. An apparatus, comprising:

a check node processing functional block that is operable to perform min** processing using a plurality of values that correspond, at least in part, to a plurality of variable node extrinsic information values, to update a check node extrinsic information value;

a variable node processing functional block that is operable to employ the updated check node extrinsic information value to update at least one variable node extrinsic information value of the plurality of variable node extrinsic information values; and

a variable bit estimation functional block that is operable to estimate a bit within an LDPC (Low Density Parity Check) coded signal using the updated at least one variable node extrinsic information value.