Circuit design tools with optimization assistance

• US 7,328,420 B1
• Filed: 11/18/2004
• Issued: 02/05/2008
• Est. Priority Date: 11/18/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wenzler, Michael, Datta, Subroto
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Bowers; Brandon
• Application Number:
  US10/993,947
• Time in Patent Office: 1,174 Days
• Field of Search: 716/11
• US Class Current: 716/102
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Computer aided design tools are provided that assist circuit designers in optimizing circuit performance. A circuit designer who is designing an integrated circuit may supply circuit design data and constraint data. Computer aided design tools may process the data to produce output data. The output data may include information on an implementation of the circuit design in a given type of integrated circuit device and may include report data on how the implementation of the circuit design is expected to perform. An optimization assistance tool analyzes the design and constraint data and the report data to identify potential problem areas. Recommendations may be provided to the circuit designer on how to address potential problems. Selectable options are displayed for the circuit designer. By selecting an appropriate option, the circuit designer can automatically launch a tool to make recommended settings adjustments.

Claims

1. A computer-implemented method for using a computer-aided design tool to provide assistance to a circuit designer, comprising:

with at least one computer aided design tool, receiving design data and constraint data for a circuit design and producing a corresponding output, wherein producing the output includes producing report data on a given implementation of the circuit design in an integrated circuit;

processing the report data and the constraint data with an optimization assistance tool, wherein processing the report data and the constraint data comprises identifying potential problems and presenting at least one selectable option to the circuit designer that allows the circuit designer to automatically launch the computer aided design tool to modify the constraint data to address the potential problems, wherein the constraint data includes placement constraints for a programmable logic device that identify which circuit nodes are located in certain regions of programmable logic when the circuit design is implemented in a particular type of programmable logic device integrated circuit;

displaying a selectable option for the circuit designer with the optimization assistance tool that the circuit designer selects to automatically launch a programmable logic device placement constraints editor; and

displaying a screen for the circuit designer with the programmable logic device placement constraints editor that the circuit designer uses to make adjustments to the placement constraints.

2. The computer-implemented method defined in claim 1 wherein processing the report data and the constraint data with the optimization assistance tool further comprises displaying a screen for the circuit designer with the optimization assistance tool that contains a selectable option that the circuit designer selects to automatically launch the computer aided design tool.

3. The computer-implemented method defined in claim 1 wherein processing the report data and the constraint data with the optimization assistance tool further comprises:

with the optimization assistance tool, displaying a screen for the circuit designer that contains a list of selectable entries, each of which corresponds to one of multiple potential problems with the given implementation of the circuit design, wherein when the circuit designer selects a given one of the selectable entries, information on the potential problem that corresponds to the selected entry is displayed for the circuit designer by the optimization assistance tool.

4. The computer-implemented method defined in claim 1 wherein processing the report data and the constraint data with the optimization assistance tool further comprises:

with the optimization assistance tool, displaying a screen of entries, each of which corresponds to one of multiple potential problems; and

displaying icons adjacent to at least some of the entries that provide information on the entries.

5. The computer-implemented method defined in claim 1 wherein processing the report data and the constraint data with the optimization assistance tool further comprises:

with the optimization assistance tool, displaying a tree of selectable problem areas, each of which has an associated icon, wherein the icons convey information on problem severity; and

with the optimization assistance tool, displaying recommendations for each of the selectable problem areas in the tree.

6. The computer-implemented method defined in claim 1 wherein processing the report data and the constraint data with the optimization assistance tool comprises:

with the optimization assistance tool, automatically launching a programmable logic device floorplan editor.

7. The computer-implemented method defined in claim 1 further comprising:

with the optimization assistance tool, displaying a screen for the circuit designer that contains a selectable link to an online help website where the circuit designer obtains help information on a recommendation made by the optimization assistance tool.

8. The computer-implemented method defined in claim 1 further comprising:

with the optimization assistance tool, displaying information for the circuit designer on recommended placement constraint settings.

9. The computer-implemented method defined in claim 1 further comprising:

with the optimization assistance tool, providing recommendations for the circuit designer on settings to adjust for certain design objects to optimize the implementation of the circuit design.

10. The computer-implemented method defined in claim 1 further comprising:

with the optimization assistance tool, providing multiple selectable on-screen options for the circuit designer each of which corresponds to a different computer aided design tool, wherein the circuit designer selects a desired one of the selectable on-screen options to direct the optimization assistance tool to launch the computer aided design tool corresponding to that selected on-screen option.

11. The computer-implemented method defined in claim 1 further comprising:

with a program in a suite of programmable logic device compiler tools, compiling the circuit design to produce the implementation of the circuit design; and

with the optimization assistance tool, identifying potential problems with the implementation of the circuit design produced using the program and providing the circuit designer with recommendations on how to modify settings for the programmable logic device compiler tools to address the potential problems.

12. The computer-implemented method defined in claim 1 further comprising displaying a selectable option for the circuit designer with the optimization assistance tool that the circuit designer selects to direct the optimization assistance tool to obtain more detail on the circuit design.

13. The computer-implemented method defined in claim 1 further comprising:

with the optimization assistance tool, identifying potential problems with the implementation of the circuit design and providing the circuit designer with recommendations on how to modify settings for the programmable logic device compiler tools to address the potential problems, wherein the recommendations for the potential problems are displayed on a screen in an order that takes into account how important the recommended changes are and how difficult it is to make the recommended changes.

14. The computer-implemented method defined in claim 1 further comprising:

with programmable logic device compiler tools, compiling the circuit design to produce the implementation of the circuit design;

with the optimization assistance tool, identifying potential problems with the implementation of the circuit design and providing the circuit designer with recommendations on how to modify settings for the programmable logic device compiler tools to address the potential problems; and

displaying a selectable option for the circuit designer with the optimization assistance tool that the circuit designer selects to direct the optimization assistance tool to automatically make the recommended settings modifications.

15. The computer-implemented method defined in claim 1 further comprising:

with the computer aided design tool, storing the circuit design data and constraint data in a database;

displaying a selectable option for the circuit designer with the optimization assistance tool that the circuit designer selects to direct the optimization assistance tool to obtain more information on the circuit design from the database; and

with the optimization assistance tool, displaying the information obtained from the database on a screen for the circuit designer.

16. The computer-implemented method defined in claim 1 wherein the constraint data includes timing constraints, the method further comprising:

with the optimization assistance tool, identifying which timing constraints can be modified to help optimize the implementation of the circuit design.

17. The computer-implemented method defined in claim 1 wherein processing the report data and the constraint data with the optimization assistance tool further comprises:

with the optimization assistance tool, automatically launching a design editor that the circuit designer can use to change the design data for the circuit design.

18. A computer readable storage medium containing program instruction which when executed cause a computer to perform a method comprising:

receiving circuit design data and constraint data from a circuit designer;

processing the circuit design data and constraint data to produce an implementation of the circuit design for an integrated circuit and report data on the implementation;

analyzing the report data to identify potential problems with the implementation;

displaying a screen for the circuit designer that contains recommendations for addressing the identified potential problems and a selectable option; and

automatically launching a computer aided design tool when the circuit designer selects the selectable option, wherein the computer aided design tool displays a screen for the circuit designer that contains information on settings to adjust to change the constraint data, wherein the constraint data includes placement constraints for a programmable logic device that identify which circuit nodes are located in certain regions of programmable logic when the circuit design is implemented in a particular type of programmable logic device integrated circuit;

displaying a selectable option for the circuit designer that the circuit designer selects to automatically launch a programmable logic device placement constraints editor; and

displaying a screen for the circuit designer with the programmable logic device placement constraints editor that the circuit designer uses to make adjustments to the placement constraints.

19. The computer readable storage medium defined in claim 18 further comprising displaying an on-screen option that the circuit designer selects to display information on design objects for which the recommendations suggest settings should be changed.