Instruction operand tracing for software debug

• US 7,328,429 B2
• Filed: 11/13/2003
• Issued: 02/05/2008
• Est. Priority Date: 11/13/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hooper, Donald F., Walker, Eric
• Primary Examiner(s): Zhen, Wei
• Assistant Examiner(s): Chen, Qing
• Application Number:
  US10/713,332
• Publication Number:
  US 20050108689A1
• Time in Patent Office: 1,545 Days
• Field of Search: 717124-135, 712/216, 712/227, 712/245, 703 13- 16, 703 20- 22
• US Class Current: 717/128
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software

Abstract

A tool that enables a user to perform instruction operand tracing during debug is presented. While executing microcode on a simulator, a history of register and memory values is saved. A graphic user interface uses these values to present a view of the microcode in a thread history. The user can use the thread history to select any given cycle time of the simulation, and switch over to a thread window (or code list view). The instruction that executed at the cycle of interest is marked in the code list view, and right-clicking on the code line, the user is given options, including an option to jump backward in time to the code line where a source variable was set and/or the option to jump forward in time to a code line that used a result variable.

Claims

1. A method comprising:

receiving a user selection of a first instruction from a list of instructions that executed during a processor simulation; and

tracing an operand in the first instruction directly to a use of the operand in a second instruction in the list of instructions by following operand dependencies between such first and second instructions,

wherein tracing comprises using attributes of the first instruction to find the second instruction and using a program counter value to look up attributes of the first instruction in an instruction operand map that provides attributes of each instruction, including instruction type and type of registers used by such instruction type for operands and to determine for each register type a physical address.

2. The method of claim 1 wherein tracing determines that the second instruction set the value of the operand as used in the first instruction as a source operand.

3. The method of claim 1 wherein tracing determines that a next use of the operand, after that of the first instruction as a destination operand, occurs in the second instruction.

4. The method of claim 1 wherein receiving comprises:

receiving a selected cycle corresponding to the first instruction.

5. The method of claim 4 further comprising:

determining the program counter value associated with the selected cycle.

6. The method of claim 5 wherein determining the program counter value comprises looking up the program counter value in a program counter history that records state change events, which are detected during simulation, with associated program counter values for each cycle in which such state change events occurred.

7. The method of claim 6 wherein tracing further comprises:

using the physical address for each register used in the first instruction to traverse the program counter history, instruction by instruction, to find a matching physical address in the second instruction.

8. The method of claim 7 wherein the microcode is intended for execution on one or more microengines in a processor simulated by the processor simulation and wherein the program counter history of more than one of the microengines is traversed.

9. The method of claim 1 wherein the instructions are instructions of a microcode and the instruction operand map is generated at microcode build time.

10. The method of claim 1 wherein determining the physical address comprises determining whether each register type is a non-I/O register or an I/O register.

11. The method of claim 10 wherein determining the physical address comprises determining whether each non-I/O register is accessed using an index register.

12. The method of claim 11 wherein the instruction operand map is used to provide the physical address for each non-I/O register that is not accessed using an index register.

13. The method of claim 12 wherein the physical address for any register determined to be an I/O register is obtained for the selected cycle from a memory reference history that records physical addresses and reference counts for each of the I/O registers that is used in a memory reference during simulation.

14. The method of claim 11 wherein the physical address for each non-I/O register that is determined to be accessed using an index register is determined by obtaining a historical value of the index register at the selected cycle from a register history that records historical values of registers for each register type as such values change during simulation.

15. The method of claim 1 wherein the instructions are intended for execution on at least one microengine of the processor simulated by the processor simulation.

16. The method of claim 15 wherein the microengine is configured to support multiple threads of execution and the instructions are intended for execution by at least one of the multiple threads of execution.

17. An article comprising:

a storage medium having stored thereon instructions that when executed by a machine result in the following;

receiving a user selection of a first instruction from a list of instructions that executed during a processor simulation; and

tracing an operand used in the first instruction directly to a use of the operand in a second instruction in the list of instructions by following operand dependencies between such first and second instructions,

wherein tracing comprises;

determining attributes of the first instruction selected by the user; and

using the attributes of the first instruction selected by the user to find the second instruction,

wherein determining attributes comprises;

using a program counter value to look up the attributes in an instruction operand map that provides attributes of each instruction, including instruction type and type of registers used by such instruction type for operands and to determine for each type of register a physical address.

18. The article of claim 17 wherein tracing determines that the second instruction set the value of the operand as used in the first instruction.

19. The article of claim 17 wherein tracing determines that a next use of the operand after that of the first instruction occurs in the second instruction.

20. A storage medium having executable instructions stored and configured to be executed by a processor, the executable instructions comprising:

executable instructions to render a window having a view of microcode instructions that executed on a processor simulator during a simulation and for which a simulation history has been collected by the processor simulator;

wherein executable instructions to render a window having the view comprises executable instructions to provide a tracing option in a menu presented to a user for one of the microcode instructions as an instruction of interest, the tracing option being usable to trace any variable used by the instruction of interest in the simulation history directly to a second instruction in which a most recent change to or next use of such variable occurred,

the executable instructions further comprising executable instructions to;

receive a user selection of the instruction of interest; and

trace an operand in the instruction of interest directly to a use of the operand in the second instruction of the microcode instructions by following operand dependencies between the instruction of interest and the second instructions,

wherein executable instructions to trace comprises executable instructions to use a program counter value to look up attributes in an instruction operand map that provides attributes of each instruction, including instruction type and type of registers used by such instruction type for operands and to determine for each type of register a physical address.

21. The storage medium of claim 20 wherein selection of the tracing option by the user causes a submenu of options available for the instruction of interest to be provided to the user, each of the options of the submenu corresponding to one of the variables used by the instruction of interest.

22. The storage medium of claim 20 further comprising executable instructions to render:

a second window in which a cycle of interest corresponding to the instruction of interest is indicated;

wherein the indication of the cycle of interest is modified to indicate a new cycle of interest corresponding to the second instruction; and

wherein the window is modified to reflect the new cycle of interest.