Technique for providing multiple stress sources in NMOS and PMOS transistors

• US 7,329,571 B2
• Filed: 08/24/2006
• Issued: 02/12/2008
• Est. Priority Date: 10/31/2005
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: HOENTSCHEL, JAN, Wei, Andy, Horstmann, Manfred, Kammler, Thorsten
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): Ahmadi, Mohsen
• Application Number:
  US11/466,802
• Publication Number:
  US 20070096195A1
• Time in Patent Office: 537 Days
• Field of Search: 438/199, 438/257, 438/231, 438/682, 257/192, 257/315, 257/344, 257/734, 257/E21.051
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

By combining a plurality of stress inducing mechanisms in each of different types of transistors, a significant performance gain may be obtained, thereby providing enhanced flexibility in adjusting product specific characteristics. For this purpose, sidewall spacers with high tensile stress may be commonly formed on PMOS and NMOS transistors, wherein a deleterious effect on the PMOS transistor may be compensated for by a corresponding compressively stressed contact etch stop layer, while the NMOS transistor comprises a contact etch stop layer with tensile stress. Furthermore, the PMOS transistor comprises an embedded strained semiconductor layer for efficiently creating compressive strain in the channel region.

Claims

1. A method, comprising:

forming a first gate electrode of a first transistor of a first type and a second gate electrode of a second transistor of a second type;

forming a strained semiconductor layer in a recess formed adjacent to said second gate electrode;

forming a first sidewall spacer structure at said first gate electrode and a second sidewall spacer structure at said second gate electrode, said first and second sidewall spacer structures having a first type of stress;

forming a first contact etch stop layer above said first transistor, said first contact etch stop layer having said first type of stress; and

forming a second contact etch stop layer above said second transistor, said second contact etch stop layer having a second type of stress other than said first type, wherein forming said second contact etch stop layer comprises selecting a magnitude of said second type of stress so as to at least compensate for said first type of stress in said second sidewall spacer structure.

2. The method of claim 1, wherein forming said first and second contact etch stop layers comprises forming one of said first and second contact etch stop layers above said first and second transistors, selectively removing a portion of said one of the first and the second contact etch stop layers from one of the first and second transistors, and forming the other one of said first and second contact etch stop layers.

3. The method of claim 1, wherein forming said first and second sidewall spacer structures comprises depositing a first spacer layer having said first type of stress and anisotropically etching said first spacer layer to form a first spacer of said first and second sidewall spacer structures.

4. The method of claim 3, wherein depositing said first spacer layer comprises adjusting one or more deposition parameters on the basis of a target value for a first specified magnitude of said first type of stress in said first sidewall spacer structure.

5. The method of claim 3, wherein forming said first and second sidewall spacer structures comprises depositing a second spacer layer having said first type of stress and anisotropically etching said second spacer layer to form a second spacer of said first and second sidewall spacer structures.

6. The method of claim 5, wherein depositing said second spacer layer comprises adjusting one or more deposition parameters on the basis of a target value for a second specified magnitude of said first type of stress in said second sidewall spacer structure.

7. The method of claim 1, wherein said magnitude of said second type of stress of said second contact etch stop layer is selected so as to over-compensate for said first type of stress in said second sidewall spacer structure.

8. The method of claim 1, further comprising forming a recess adjacent to said first gate electrode and forming said semiconductor layer commonly in said recesses located adjacent to said first and second gate electrodes.

9. The method of claim 8, wherein said semiconductor layer in said first transistor is provided as a substantially relaxed semiconductor layer.

10. The method of claim 1, further comprising forming an etch stop layer above said first and second transistors prior to forming said first and second contact etch stop layers, and removing said etch stop layer at least above said second transistor prior to forming said second contact etch stop layer.

11. The method of claim 10, wherein said etch stop layer comprises a stressed layer having the first type of stress.

12. The method of claim 1, wherein the strained semiconductor layer has the second type of stress.

13. The method of claim 1, wherein the strained semiconductor layer has the second type of stress.

14. A method, comprising:

forming a first gate electrode of a first transistor of a first type and a second gate electrode of a second transistor of a second type;

forming a strained semiconductor layer in a recess formed adjacent to said second gate electrode;

forming a first sidewall spacer structure at said first gate electrode and a second sidewall spacer structure at said second gate electrode, said first and second sidewall spacer structures having a first type of stress, wherein forming said first and second sidewall spacer structures comprises depositing a first spacer layer having said first type of stress, anisotropically etching said first spacer layer to form a first spacer of said first and second sidewall spacer structures, depositing a second spacer layer having said first type of stress, and anisotropically etching said second spacer layer to form a second spacer of said first and second sidewall spacer structures;

forming a first contact etch stop layer above said first transistor, said first contact etch stop layer having said first type of stress; and

forming a second contact etch stop layer above said second transistor, said second contact etch stop layer having a second type of stress other than said first type.

15. The method of claim 14, wherein forming said first and second sidewall spacer structures comprises adjusting one or more deposition parameters for depositing the first spacer layer on the basis of a target value for a first specified magnitude of said first type of stress in said first sidewall spacer structure.

16. The method of claim 15, wherein forming said first and second sidewall spacer structures comprises adjusting one or more deposition parameters for depositing the second spacer layer on the basis of a target value for a second specified magnitude of said first type of stress in said second sidewall spacer structure.

17. The method of claim 14, wherein said magnitude of said second type of stress of said second contact etch stop layer is selected so as to over-compensate for said first type of stress in said second sidewall spacer structure.

18. The method of claim 14, further comprising forming an etch stop layer above said first and second transistors prior to forming said first and second contact etch stop layers, wherein said etch stop layer comprises a stressed layer having the first type of stress, and removing said etch stop layer at least above said second transistor prior to forming said second contact etch stop layer.

19. The method of claim 14, wherein the strained semiconductor layer has the second type of stress.

20. A method, comprising:

forming a first gate electrode of a first transistor of a first type and a second gate electrode of a second transistor of a second type;

forming a strained semiconductor layer in a recess formed adjacent to said second gate electrode;

forming a first sidewall spacer structure at said first gate electrode and a second sidewall spacer structure at said second gate electrode, said first and second sidewall spacer structures having a first type of stress;

forming a first contact etch stop layer above said first transistor, said first contact etch stop layer having said first type of stress;

forming a second contact etch stop layer above said second transistor, said second contact etch stop layer having a second type of stress other than said first type;

forming an etch stop layer above said first and second transistors prior to forming said first and second contact etch stop layers; and

removing said etch stop layer at least above said second transistor prior to forming said second contact etch stop layer.

21. The method of claim 20, wherein said etch stop layer comprises a stressed layer having the first type of stress.

22. The method of claim 20, wherein the strained semiconductor layer has the second type of stress.

23. The method of claim 20, wherein said magnitude of said second type of stress of said second contact etch stop layer is selected so as to over-compensate for said first type of stress in said second sidewall spacer structure.

24. The method of claim 23, wherein said semiconductor layer in said first transistor is provided as a substantially relaxed semiconductor layer.

25. The method of claim 20, further comprising forming a recess adjacent to said first gate electrode and forming said semiconductor layer commonly in said recesses located adjacent to said first and second gate electrodes.

26. A method, comprising:

forming a first gate electrode of a first transistor of a first type and a second gate electrode of a second transistor of a second type;

forming a strained semiconductor layer in a recess formed adjacent to said second gate electrode;

forming a first sidewall spacer structure at said first gate electrode and a second sidewall spacer structure at said second gate electrode, said first and second sidewall spacer structures having a first type of stress, wherein forming said first and second sidewall spacer structures comprises depositing a first spacer layer having said first type of stress, adjusting one or more deposition parameters for depositing the first spacer layer on the basis of a target value for a first specified magnitude of said first type of stress in said first sidewall spacer structure, and anisotropically etching said first spacer layer to form a first spacer of said first and second sidewall spacer structures;

forming a first contact etch stop layer above said first transistor, said first contact etch stop layer having said first type of stress; and

forming a second contact etch stop layer above said second transistor, said second contact etch stop layer having a second type of stress other than said first type.

27. The method of claim 26, wherein forming said first and second sidewall spacer structures comprises depositing a second spacer layer having said first type of stress and anisotropically etching said second spacer layer to form a second spacer of said first and second sidewall spacer structures.

28. The method of claim 27, wherein depositing said second spacer layer comprises adjusting one or more deposition parameters on the basis of a target value for a second specified magnitude of said first type of stress in said second sidewall spacer structure.

29. The method of claim 26, wherein said magnitude of said second type of stress of said second contact etch stop layer is selected so as to over-compensate for said first type of stress in said second sidewall spacer structure.