Method for fabricating a semiconductor device

• US 7,329,599 B1
• Filed: 03/16/2005
• Issued: 02/12/2008
• Est. Priority Date: 03/16/2005
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wirbeleit, Frank, Bolom, Tibor, Van Meer, Johannes
• Primary Examiner(s): Baumeister, B. William
• Assistant Examiner(s): Anya, Igwe U.
• Application Number:
  US11/082,618
• Time in Patent Office: 1,063 Days
• Field of Search: 438/627, 257/E21.199
• US Class Current: 438/627
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76859 by ion implantation
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Methods are provided for semiconductor devices having low contact resistance. The method in accordance with one embodiment of the invention comprises forming an insulating layer overlying a semiconductor substrate, the semiconductor substrate having a device region therein. An opening is formed through the insulating layer to expose a portion of the device region, and the portion of the device region is then electrically contacted by a metallic liner layer. To reduce the resistance of the liner layer and hence the contact, ions of a conductivity determining impurity are implanted into the metallic liner layer. A metal layer is then deposited overlying the metallic liner layer to fill the opening through the insulating layer and to form a conductive plug.

Claims

1. A method for fabricating a semiconductor device comprising the steps of:

forming an insulating layer overlying a semiconductor substrate, the semiconductor substrate having a device region therein;

forming an opening through the insulating layer to expose a portion of the device region;

contacting the portion of the device region with a first metal layer;

forming an electrically conductive barrier layer overlying the first metal layer, and thereby forming an interface between the first metal layer and the electrically conductive barrier layer, the first metal layer and the electrically conductive barrier layer cooperating to form a metallic liner;

implanting ions of a conductivity determining impurity into the conductive barrier layer, the ions being implanted under implantation conditions that produce a peak implant concentration within the metallic liner substantially at the interface between the first metal layer and the electrically conductive barrier layer; and

depositing a metal layer overlying the metallic liner and filling the opening through the insulating layer.

2. The method of claim 1 wherein the step of contacting the portion of the device region with the first metal layer comprises depositing a layer of titanium in electrical contact with the portion of the device region.

3. The method of claim 2 wherein the step of forming a layer of electrically conductive barrier layer material comprises the step of forming a layer of titanium nitride.

4. The method of claim 3 wherein the step of depositing a layer of titanium is performed by a process of physical vapor deposition, and the step of forming a layer of titanium nitride is performed by a process selected from the group consisting of physical vapor deposition, chemical vapor deposition and atomic layer deposition.

5. The method of claim 4 wherein the step of forming a layer of titanium nitride comprises the step of chemical vapor depositing a layer of titanium nitride in a multi-step deposition process.

6. The method of claim 1 wherein the device region comprises an impurity doped region having a surface and wherein the method further comprising the step of forming a layer of metal silicide at the surface of the impurity doped region and wherein the metallic barrier layer electrically contacts the metal silicide.

7. The method of claim 1 wherein the step of implanting ions of a conductivity determining impurity comprises the step of implanting ions of a group 15 element.

8. The method of claim 7 wherein the step of implanting ions of a conductivity determining impurity comprises the step of implanting arsenic ions.

9. A method for fabricating a semiconductor device in and on a silicon substrate comprising the steps of:

forming an impurity doped region in the silicon substrate, the impurity doped region having a surface;

forming a metal silicide region at the surface of the impurity doped region;

forming an insulator layer overlying the silicon substrate;

forming an opening in the insulator layer to expose a portion of the metal silicide region;

depositing a titanium layer into the opening and contacting the metal silicide region;

forming a titanium nitride barrier layer overlying the titanium layer, and thereby forming an interface between the titanium layer and the titanium nitride barrier layer, the titanium layer and the titanium nitride barrier layer cooperating to form a metallic liner;

implanting ions of a conductivity determining group 15 element into the titanium nitride barrier layer, the ions being implanted under implantation conditions that produce a peak implant concentration within the metallic liner substantially at the interface between the titanium layer and the titanium nitride barrier layer; and

depositing a material comprising tungsten in contact with the titanium nitride barrier layer to fill the opening.

10. The method of claim 9 wherein the metal silicide region comprises a metal silicide selected from the group consisting of nickel silicide, cobalt silicide, nickel/platinum silicide, platinum silicide, titanium silicide, and rhodium silicide.

11. The method of claim 9 wherein the step of implanting ions comprises the step of implanting ions of elements from the group consisting of phosphorus and arsenic.

12. The method of claim 9 wherein the step of depositing a material comprising tungsten comprises the step of chemical vapor depositing a layer of tungsten by a reaction of tungsten hexafluoride and hydrogen.

13. A method for fabricating a semiconductor device in and overlying a semiconductor substrate, the method comprising the steps of:

forming an impurity doped region in the semiconductor substrate;

forming an insulating layer overlying the semiconductor substrate and the impurity doped region;

photolithographically patterning and etching the insulating layer to form an opening through the insulating layer to expose a portion of the impurity doped region, the opening bounded by walls of the insulator;

depositing a first metal layer into the opening, along the walls, and electrically contacting the portion of the impurity doped region;

forming an electrically conductive barrier layer overlying the first metal layer, the electrically conductive barrier layer having a thickness insufficient to fill the opening, and thereby forming an interface between the first metal layer and the electrically conductive barrier layer, the first metal layer and the electrically conductive barrier layer cooperating to form a metallic liner;

ion implanting the electrically conductive barrier layer with ions of a conductivity determining impurity, the ions being implanted with an implant energy that produces a peak implant concentration within the metallic liner substantially at the interface between the first metal layer and the electrically conductive barrier layer; and

depositing a tungsten plug material overlying the electrically conductive barrier layer to fill the opening.

14. The method of claim 13 further comprising the step of forming a metal silicide layer at a surface of the impurity doped region and wherein the first metal layer physically contacts the metal silicide layer.

15. The method of claim 13 wherein the step of depositing a first metal layer comprises the step of depositing a layer of titanium and the step of forming an electrically conductive barrier layer comprises the step of forming a layer of titanium nitride, the layer of titanium and the layer of titanium nitride forming the interface therebetween.

16. The method of claim 15 wherein the step of ion implanting comprises the step of ion implanting the titanium nitride layer with arsenic ions.

17. The method of claim 15 wherein the step of depositing a layer of titanium comprises the step of depositing a layer of titanium by physical vapor deposition, the step of forming a layer of titanium nitride comprises the step of depositing a layer of titanium nitride by a process of chemical vapor deposition, and the step of depositing a tungsten plug material comprises the step of depositing a layer of tungsten by chemical vapor deposition.

18. The method of claim 13 wherein the step of depositing a first metal layer comprises the step of depositing a layer of tantalum and the step of forming an electrically conductive barrier layer comprises the step of forming a layer of tantalum nitride.