Nonplanar transistors with metal gate electrodes

• US 7,329,913 B2
• Filed: 12/27/2004
• Issued: 02/12/2008
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Doyle, Brian S., Brask, Justin K.
• Primary Examiner(s): Doan; Theresa T.
• Application Number:
  US11/023,881
• Publication Number:
  US 20050156171A1
• Time in Patent Office: 1,142 Days
• Field of Search: 257287-288, 257329-332, 257/347, 257/401
• US Class Current: 257/287
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A semiconductor device comprising:

a semiconductor body formed on an insulating substrate, said semiconductor body having a top surface and a first and second laterally opposite sidewalls;

a gate dielectric formed on said top surface of said semiconductor body and on said first and second laterally opposite sidewalls of said semiconductor body;

a gate electrode formed on said gate dielectric on said top surface of said semiconductor body and adjacent to said gate dielectric on said first and said second laterally opposite sidewalls of said semiconductor body, wherein said gate electrode comprises a metal film formed directly adjacent to said gate dielectric;

a pair of source/drain regions formed in said semiconductor body on opposite sides of said gate electrode; and

a pair of sidewall spacers formed along opposite sides of said gate electrode and wherein said gate dielectric is located between said pair of sidewall spacers and said gate electrode.

2. The semiconductor device of claim 1 wherein said gate electrode comprises only said metal film.

3. The semiconductor device of claim 1 wherein said gate electrode further comprises a doped silicon film formed on said metal film.

4. The semiconductor device of claim 3 wherein said metal film is formed to a thickness between 25-100Å

and said doped silicon film is formed to a thickness between 500-3000Å

.

5. The semiconductor device of claim 1 wherein said semiconductor body is silicon, and said source/drain regions have p type conductivity and said metal film has a work function between 4.9-5.2 eV.

6. The semiconductor device of claim 1 wherein said semiconductor body is silicon and said source/drain regions have p type conductivity and said metal film is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, with a workfunction between about 4.9 eV and 5.2 eV.

7. The semiconductor device of claim 1 wherein said semiconductor body is formed from silicon and said source/drain regions have n type conductivity and said metal film has a work function between 3.9 eV and 4.2 eV.

8. The semiconductor device of claim 1 wherein said semiconductor body is silicon and said source/drain regions have n type conductivity and said metal film is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, with a workfunction between about 3.9 eV and about 4.2 eV.

9. The semiconductor device of claim 1 wherein said metal film is selected from the metal having a work function between 4.2 to 4.8 eV.

10. The semiconductor device of claim 1 wherein said gate dielectric comprises silicon dioxide.

11. The semiconductor device of claim 1 wherein said gate dielectric is selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, PZT, BST, aluminum oxide, and silicate thereof.

12. The semiconductor device of claim 1 wherein said semiconductor body is selected from the group consisting of germanium, silicon germanium, gallium arsenide, InSb, GaP, GaSb, and carbon nanotubes.

13. A semiconductor integrated circuit comprising:

a first semiconductor device comprising;

a first semiconductor body formed on an insulating substrate, said first semiconductor body having a top surface and a first and second laterally opposite sidewalls;

a first gate dielectric formed on said top surface of said first semiconductor body and on said first and second laterally opposite sidewalls of said first semiconductor body;

a first gate electrode formed on said first gate dielectric on said top surface of said first semiconductor body and adjacent to said gate dielectric on said first and second laterally opposite sidewalls of said semiconductor body, wherein said first gate electrode comprises a first metal film formed directly adjacent to said first gate dielectric;

a first pair of source/drain regions having p type conductivity formed in said first semiconductor body on opposite sides of said first gate electrode;

a first pair of sidewall spacers formed along opposite sides of said first gate electrode and wherein said first gate dielectric is formed between said first pair of sidewall spacers and said first gate electrode; and

a second semiconductor device comprising;

a second semiconductor body formed on said insulating substrate, said second semiconductor body having a top surface and a first and second laterally opposite sidewalls;

a second gate dielectric formed on said top surface of said second semiconductor body and on said first and second laterally opposite sidewalls of said second semiconductor body;

a second gate electrode formed on said second gate dielectric on said top surface of said second semiconductor body and adjacent to said gate dielectric on said first and second laterally opposite sidewalls of said second semiconductor body, wherein second gate electrode comprises a second metal film formed directly adjacent to said second gate dielectric wherein said second metal film is different than said first metal film;

a second pair of source/drain regions having n type conductivity formed in said second semiconductor body on opposite sides of said second gate electrode; and

a second pair of sidewall spacers formed along opposite sides of said second gate electrode and wherein said second gate dielectric is formed between said second pair of sidewall spacers and said second gate electrode.

14. The semiconductor device of claim 13 wherein said first metal film has a work function between 4.9 eV and 5.2 eV and said second metal film has a work function between 3.9 eV and 4.2 eV.

15. The integrated circuit of claim 13 wherein said first metal film is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, with a workfunction between about 4.9 eV and 5.2 eV and wherein said second metal film is selected from group consisting of hafnium, zirconium, titanium, tantalum, aluminum, with a workfunction between about 3.9 eV and about 4.2 eV.

16. The integrated circuit of claim 13 wherein said first metal film has a work function of approximately 1.0 eV greater than the work function of said second metal film.

17. The integrated circuit of claim 13 wherein said first gate dielectric and said second gate dielectric are selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, PZT, BST, aluminum oxide, and silicate thereof.

18. The integrated circuit of claim 13 wherein said first semiconductor body and said second semiconductor body are selected from the group consisting of germanium, silicon germanium, gallium arsenide, InSB, GaP, GaSb, and carbon nanotubes.