Permeable capacitor electrode

• US 7,329,917 B2
• Filed: 04/27/2006
• Issued: 02/12/2008
• Est. Priority Date: 08/29/2003
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Walker, Michael A., Patraw, Robert D.
• Primary Examiner(s): Sarkar; Asok K.
• Assistant Examiner(s): Yevsikov; Victor V.
• Application Number:
  US11/414,661
• Publication Number:
  US 20060192239A1
• Time in Patent Office: 656 Days
• Field of Search: 438/253, 438/396, 438/239, 438/257, 438/972, 257/303, 257/306, 257/E21.19
• US Class Current: 257/303
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: Y10S 438/972 Stored charge erasure

Abstract

The present teachings describe a container capacitor that utilizes an etchant permeable lower electrode for the formation of single or double-sided capacitors without excessive etching back of the periphery of the use of sacrificial spacers. The present teachings further describe a method of forming at least one capacitor structure on a substrate. For example, the method comprises forming at least one recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the at least one recess, and defining at least one lower electrode within the at least one recess formed in the substrate by removing at least a portion of the first conductive layer. The method further comprises diffusing an etchant through the at least one lower electrode so as to remove at least a portion of the substrate to thereby at least partially isolate the at least one lower electrode. The method still further comprises depositing a dielectric layer on the at least one isolated lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.

Claims

1. A capacitive structure comprising:

a semiconductor substrate, wherein the substrate comprises an inter layer dielectric layer formed of borophosphosilicate glass (BPSG) that is formed on the substrate;

a first electrode formed adjacent the substrate, wherein the first electrode is formed so that at least portions of the first electrode are permeable to etching so as to allow etching of regions of the substrate adjacent the first electrode;

a dielectric layer formed adjacent the first electrode; and

a second electrode adjacent the dielectric layer such that the first and second electrode define two separate plates of the capacitive structure.

2. The structure of claim 1, wherein the first electrode is formed of a layer of conductive material having a thickness that is selected to permit etching of the substrate through the first electrode.

3. The structure of claim 2, wherein the first electrode is formed of a material selected from the group consisting of polysilicon, TiN, WSi, and a metal alloy that includes copper, aluminum, silver, gold, platinum or rhodium.

4. The structure of claim 1, wherein the first electrode is formed of a material that includes impurities which can be selectively removed to result in the first electrode being permeable or porous to etching.

5. The structure of claim 4, wherein the first electrode is formed of a partially oxidized polysilicon wherein the oxide is selectively removed so as to form the permeable or porous first electrode.

6. The structure of claim 4, wherein the first electrode is formed of a doped TiN material wherein the dopant can be selectively removed so as to form the permeable or porous first electrode.

7. The structure of claim 1, wherein the first electrode has a first and second vertical side walls and an interconnecting lower section and wherein the first and second sidewalls are formed so as to be permeable to etching so as to allow etching of regions of the substrate adjacent the first and second side walls.

8. An assembly of a plurality of capacitive structures comprising:

an insulating layer, wherein the insulating layer comprises an inter layer dielectric layer formed of borophosphosilicate glass (BPSG) that is formed on a semiconductor substrate;

a plurality of first electrodes positioned in the insulating layer, wherein the plurality of first electrodes are formed so as to permit etching of the insulating layer surrounding the plurality of first electrodes;

a plurality of dielectric layers respectively positioned adjacent the plurality of first electrodes;

a plurality of second electrodes respectively positioned adjacent he plurality of first electrodes so as to form the plurality of capacitive structures.

9. The assembly of claim 8, wherein the plurality of capacitive structures define an array of capacitive structures.

10. The assembly of claim 8, wherein the inter layer dielectric layer is interposed between adjacent capacitive structures.

11. The assembly of claim 8, wherein the plurality of first electrodes are formed of a layer of conductive material having a thickness that is selected to permit etching of the insulating layer through the plurality of first electrodes.

12. The assembly of claim 11, wherein the plurality of first electrodes are formed of a material selected from the group consisting of polysilicon, TiN, WSi, and a metal alloy that includes copper, aluminum, silver, gold, platinum or rhodium.

13. The assembly of claim 8, wherein the plurality of first electrodes are formed of a material that includes impurities which can be selectively removed to result in the plurality of first electrodes being permeable or porous to etching.

14. The assembly of claim 13, wherein the plurality of first electrodes are formed of a partially oxidized polysilicon wherein the oxide is selectively removed so as to form the permeable or porous plurality of first electrodes.

15. The assembly of claim 13, wherein the plurality of first electrodes are formed of a doped TiN material wherein the dopant can be selectively removed so as to form the permeable or porous plurality of first electrodes.

16. The assembly of claim 8, wherein the plurality of first electrodes has a first and second vertical side walls and an interconnecting lower section and wherein the first and second sidewalls are formed so as to be permeable to etching so as to allow etching of regions of the substrate adjacent the first and second side walls.