Top layers of metal for high performance IC's

• US 7,329,954 B2
• Filed: 05/17/2005
• Issued: 02/12/2008
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Mou-Shiung Lin
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US11/130,917
• Publication Number:
  US 20050245067A1
• Time in Patent Office: 1,001 Days
• Field of Search: 257/758, 257/760, 257/781, 257/784, 257/774
• US Class Current: 257/758
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5225 : Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/53295 : Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 428/12542 : More than one such component
• CPC Class Codes: Y10T 428/12993 : Surface feature [e.g., rough, mirror]

Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims

1. A semiconductor chip comprising:

a silicon substrate;

multiple semiconductor devices in or over said silicon substrate;

an interconnecting metallization structure over said silicon substrate, wherein said interconnecting metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a separating, passivation layer over said interconnecting metallization structure and over said dielectric layer, wherein said separating, passivation layer comprises multiple inorganic layers and an organic layer, said organic layer being over said multiple inorganic layers, wherein said organic layer has a thickness greater than that of said dielectric layer, and wherein a first opening in said separating, passivation layer exposes a first contact point of said interconnecting metallization structure, and a second opening in said separating, passivation layer exposes a second contact point of said interconnecting metallization structure, wherein said first contact point is separate from said second contact point; and

an upper metallization structure over said separating, passivation layer and over said first and second contact points, wherein said upper metallization structure comprises an electroplated metal, and wherein a connecting portion of said upper metallization structure connects at least one portion of said interconnecting metallization structure with at least one other portion of said interconnecting metallization structure through said first and second openings and through said first and second contact points, wherein said connecting portion of said upper metallization structure comprises a signal distribution interconnect.

2. The semiconductor chip of claim 1, wherein said interconnecting metallization structure comprises a sub-micron metal line.

3. The semiconductor chip of claim 1, wherein one of said multiple inorganic layers comprises nitride.

4. The semiconductor chip of claim 1, wherein one of said multiple inorganic layers comprises oxide.

5. The semiconductor chip of claim 1, wherein one of said multiple inorganic layers has a thickness between about 0.15 μ

m and 2 μ

m.

6. The semiconductor chip of claim 1, wherein said multiple inorganic layers comprise an oxide layer and a nitride layer.

7. The semiconductor chip of claim 6, wherein said nitride layer is over said oxide layer.

8. The semiconductor chip of claim 1, wherein said upper metallization structure further comprises an electroless metal.

9. The semiconductor chip of claim 1, wherein said upper metallization structure further comprises a sputtered metal.

10. The semiconductor chip of claim 1, wherein said upper metallization structure further comprises a CVD metal.

11. The semiconductor chip of claim 1, wherein said upper metallization structure further comprises a damascene metal.

12. The semiconductor chip of claim 1, wherein said electroplated metal comprises copper.

13. The semiconductor chip of claim 1, wherein said upper metallization structure further comprises nickel.

14. The semiconductor chip of claim 1, wherein said upper metallization structure further comprises aluminum.

15. The semiconductor chip of claim 1, wherein said upper metallization structure further comprises chromium.

16. The semiconductor chip of claim 1, wherein said upper metallization structure comprises one or more upper metal layers, and at least one of said one or more upper metal layers has a thickness greater than each of said first and second metal layers.

17. The semiconductor chip of claim 1, wherein said organic layer has a thickness greater than a total thickness of said multiple inorganic layers.

18. The semiconductor chip of claim 1, wherein said organic layer comprises a photosensitive polymer.

19. The semiconductor chip of claim 1, wherein said organic layer comprises a non-photosensitive polymer.

20. The semiconductor chip of claim 1, wherein said organic layer comprises polymer.

21. The semiconductor chip of claim 1, wherein said organic layer comprises polyimide.

22. The semiconductor chip of claim 1, wherein said organic layer comprises benzocyclobutene (BCB).

23. The semiconductor chip of claim 1, wherein said organic layer has a thickness between about 2 μ

m and 30 μ

m.

24. The semiconductor chip of claim 1 further comprising an upper organic layer, wherein said upper metallization structure comprises multiple upper metal layers, and said upper organic layer is between neighboring two of said multiple upper metal layers.

25. The semiconductor chip of claim 24, wherein said upper organic layer comprises polymer.

26. The semiconductor chip of claim 24, wherein said upper organic layer comprises polyimide.

27. The semiconductor chip of claim 1 further comprising an upper organic layer, wherein said upper metallization structure comprises an upper metal layer, and said upper organic layer is over said upper metal layer.

28. The semiconductor chip of claim 27, wherein said upper organic layer comprises polymer.

29. The semiconductor chip of claim 1 further comprising an upper organic layer, wherein said upper metallization structure comprises one or more upper metal layers, and said upper organic layer is over a top-most one of said one or more upper metal layers.

30. The semiconductor chip of claim 29, wherein said upper organic layer comprises polymer.

31. The semiconductor chip of claim 1, and wherein said connecting portion is connected to said first and second contact points through said first and second openings.

32. The semiconductor chip of claim 1, wherein a size of said first contact point exposed by said first opening is between about 0.3 μ

m and 5 μ

m.

33. The semiconductor chip of claim 1, wherein a diameter of said first opening is between about 0.5 μ

m and 3 μ

m.

34. The semiconductor chip of claim 1, wherein said first contact point comprises copper.

35. The semiconductor chip of claim 1, wherein said first contact point comprises aluminum.

36. The semiconductor chip of claim 1, wherein said first contact point comprises tungsten.

37. The semiconductor chip of claim 1, wherein said first contact point comprises an electroplated metal.

38. The semiconductor chip of claim 1, wherein said upper metallization structure comprises a contact pad capable of having a bump formed thereon.

39. The semiconductor chip of claim 1, wherein said upper metallization structure comprises a contact pad capable of having a solder bump formed thereon.

40. The semiconductor chip of claim 1, wherein said upper metallization structure comprises a contact pad capable of being wirebonded thereto.

41. The semiconductor chip of claim 1, wherein said interconnecting metallization structure comprises copper, aluminum, or tungsten.

42. The semiconductor chip of claim 1, wherein said multiple semiconductor devices comprise multiple transistors.

43. The semiconductor chip of claim 1, wherein said multiple semiconductor devices comprise polysilicon.

44. The semiconductor chip of claim 1, wherein said connecting portion connects at least one of said multiple semiconductor devices with at least another one of said multiple semiconductor devices through said interconnecting metallization structure.

45. The semiconductor chip of claim 1, wherein said signal distribution interconnect comprises a clock distribution network.

46. The semiconductor chip of claim 1, wherein said connecting portion of said upper metallization structure comprises a signal line or a signal plane.

47. The semiconductor chip of claim 1, wherein said upper metallization structure comprises one or more upper metal layers, and wherein said one or more upper metal layers are patterned to accommodate specific circuit design.

48. A semiconductor wafer comprising:

a silicon substrate;

multiple semiconductor devices in or over said silicon substrate;

an interconnecting metallization structure over said silicon substrate, wherein said interconnecting metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a separating, passivation layer over said interconnecting metallization structure and over said dielectric layer, wherein said separating, passivation layer comprises multiple inorganic layers and an organic layer, said organic layer being over said multiple inorganic layers, wherein said organic layer has a thickness greater than that of said dielectric layer, and wherein a first opening in said separating, passivation layer exposes a first contact point of said interconnecting metallization structure, and a second opening in said separating, passivation layer exposes a second contact point of said interconnecting metallization structure, wherein said first contact point is separate from said second contact point; and

an upper metallization structure over said separating, passivation layer and over said first and second contact points, wherein said upper metallization structure comprises an electroplated metal, and wherein a connecting portion of said upper metallization structure connects multiple portions of said interconnecting metallization structure within a chip through said first and second openings and through said first and second contact points, wherein said connecting portion of said upper metallization structure comprises a signal distribution interconnect.

49. The semiconductor wafer of claim 48, wherein said interconnecting metallization structure comprises a sub-micron metal line.

50. The semiconductor wafer of claim 48, wherein one of said multiple inorganic layers comprises nitride.

51. The semiconductor wafer of claim 48, wherein one of said multiple inorganic layers comprises oxide.

52. The semiconductor wafer of claim 48, wherein one of said multiple inorganic layers has a thickness between about 0.15 μ

m and 2 μ

m.

53. The semiconductor wafer of claim 48, wherein said multiple inorganic layers comprise an oxide layer and a nitride layer.

54. The semiconductor wafer of claim 53, wherein said nitride layer is over said oxide layer.

55. The semiconductor wafer of claim 48, wherein said upper metallization structure further comprises an electroless metal.

56. The semiconductor wafer of claim 48, wherein said upper metallization structure further comprises a sputtered metal.

57. The semiconductor wafer of claim 48, wherein said upper metallization structure further comprises a CVD metal.

58. The semiconductor wafer of claim 48, wherein said upper metallization structure further comprises a damascene metal.

59. The semiconductor wafer of claim 48, wherein said electroplated metal comprises copper.

60. The semiconductor wafer of claim 48, wherein said upper metallization structure further comprises nickel.

61. The semiconductor wafer of claim 48, wherein said upper metallization structure further comprises aluminum.

62. The semiconductor wafer of claim 48, wherein said upper metallization structure further comprises chromium.

63. The semiconductor wafer of claim 48, wherein said upper metallization structure comprises one or more upper metal layers, and at least one of said one or more upper metal layers has a thickness greater than each of said first and second metal layers.

64. The semiconductor wafer of claim 48, wherein said organic layer has a thickness greater than a total thickness said multiple inorganic layers.

65. The semiconductor wafer of claim 48, wherein said organic layer comprises a photosensitive polymer.

66. The semiconductor wafer of claim 48, wherein said organic layer comprises a non-photosensitive polymer.

67. The semiconductor wafer of claim 48, wherein said organic layer comprises polymer.

68. The semiconductor wafer of claim 48, wherein said organic layer comprises polyimide.

69. The semiconductor wafer of claim 48, wherein said organic layer comprises benzocyclobutene (BCB).

70. The semiconductor wafer of claim 48, wherein said organic layer has a thickness between about 2 μ

m and 30 μ

m.

71. The semiconductor wafer of claim 48 further comprising an upper organic layer, wherein said upper metallization structure comprises multiple upper metal layers, and said upper organic layer is between neighboring two of said multiple upper metal layers.

72. The semiconductor wafer of claim 71, wherein said upper organic layer comprises polymer.

73. The semiconductor wafer of claim 71, wherein said upper organic layer comprises polyimide.

74. The semiconductor wafer of claim 48 further comprising an upper organic layer, wherein said upper metallization structure comprises an upper metal layer, and said upper organic layer is over said upper metal layer.

75. The semiconductor wafer of claim 74, wherein said upper organic layer comprises polymer.

76. The semiconductor wafer of claim 48 further comprising an upper organic layer, wherein said upper metallization structure comprises one or more upper metal layers, and said upper organic layer is over a top-most one of said one or more upper metal layers.

77. The semiconductor wafer of claim 76, wherein said upper organic layer comprises polymer.

78. The semiconductor wafer of claim 48, wherein said connecting portion is connected to said first and second contact points through said first and second openings.

79. The semiconductor wafer of claim 48, wherein a size of said first contact point exposed by said first opening is between about 0.3 μ

m and 5 μ

m.

80. The semiconductor wafer of claim 48, wherein a diameter of said first opening is between about 0.5 μ

m and 3 μ

m.

81. The semiconductor wafer of claim 48, wherein said first contact point comprises copper.

82. The semiconductor wafer of claim 48, wherein said first contact point comprises aluminum.

83. The semiconductor wafer of claim 48, wherein said first contact point comprises tungsten.

84. The semiconductor wafer of claim 48, wherein said first contact point comprises electroplated metal.

85. The semiconductor wafer of claim 48, wherein said upper metallization structure comprises a contact pad capable of having a bump formed thereon.

86. The semiconductor wafer of claim 48, wherein said upper metallization structure comprises a contact pad capable of having a solder bump formed thereon.

87. The semiconductor wafer of claim 48, wherein said upper metallization structure comprises a contact pad capable of being wirebonded thereto.

88. The semiconductor wafer of claim 48, wherein said interconnecting metallization structure comprises copper, aluminum, or tungsten.

89. The semiconductor wafer of claim 48, wherein said multiple semiconductor devices comprise multiple transistors.

90. The semiconductor wafer of claim 48, wherein said multiple semiconductor devices comprise polysilicon.

91. The semiconductor wafer of claim 48, wherein said connecting portion connects at least one of said multiple semiconductor devices with at least another one of said multiple semiconductor devices through said interconnecting metallization structure.

92. The semiconductor wafer of claim 48, wherein said signal distribution interconnect comprises a clock distribution network.

93. The semiconductor wafer of claim 48, wherein said connecting portion of said upper metallization structure comprises a signal line or a signal plane.

94. The semiconductor wafer of claim 48, wherein a photolithography process is performed after forming said multiple inorganic layers over said interconnecting metallization structure.

95. The semiconductor wafer of claim 48, wherein said upper metallization structure comprises one or more upper metal layers, and said one or more upper metal layers are patterned to accommodate specific circuit design.