Sense amplifier circuit and method of operation
First Claim
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1. A semiconductor memory device, comprising:
- a drive high circuit that drives at least one bit line coupled to a plurality of memory cells toward a high sense voltage in a sense operation according to a sensed data value, the drive high circuit comprising at least one pull-up insulated gate field effect transistor (FET) of a first conductivity type having a body biased to a boosted high voltage;
a logic section comprising a plurality of transistors of the first conductivity type having bodies biased to a high supply voltage; and
a condition sense circuit that increases the boosted high voltage to a level above the high supply voltage when an operating condition is determined to be outside a predetermined limit, the operating condition being selected from the group consisting of an operating temperature, operating voltage, and manufacturing process variations.
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Abstract
In one arrangement, a semiconductor memory device can include a sense amplifier circuit (300) having drive high transistors (P30/P31), drive low transistors (N31/N32) and equalization transistors (N33-N35). Such transistors can have a body bias (VbiasN, VbiasP) that varies according to the operation conditions of the semiconductor memory device. Such variations can include any of: manufacturing process variations, operating temperature, or operating voltage.
64 Citations
20 Claims
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1. A semiconductor memory device, comprising:
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a drive high circuit that drives at least one bit line coupled to a plurality of memory cells toward a high sense voltage in a sense operation according to a sensed data value, the drive high circuit comprising at least one pull-up insulated gate field effect transistor (FET) of a first conductivity type having a body biased to a boosted high voltage; a logic section comprising a plurality of transistors of the first conductivity type having bodies biased to a high supply voltage; and a condition sense circuit that increases the boosted high voltage to a level above the high supply voltage when an operating condition is determined to be outside a predetermined limit, the operating condition being selected from the group consisting of an operating temperature, operating voltage, and manufacturing process variations. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor memory device, comprising:
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a sense amplifier circuit comprising first and second transistors of a first conductivity type cross coupled between sense amplifier nodes and formed in a first substrate section of a second conductivity type, first and second transistors of a second conductivity type cross coupled between the sense amplifiers nodes and formed in a second substrate section of a first conductivity type; and a bias voltage control circuit coupled to at least the first substrate section that varies a bias voltage to the first substrate section based on at least one operating condition of the semiconductor memory device. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A method of activating a sense amplifier circuit of a semiconductor memory device, comprising the steps of:
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sensing a condition of the semiconductor memory device; and modulating the threshold voltage of at least a first pair of sense transistors by biasing a substrate containing the first pair of sense transistors to a potential outside a power supply voltage range, the power supply voltage range being the range between a high power supply voltage and low power supply voltage received by the semiconductor memory device at external connections, the first pair of sense transistors being cross coupled between sense nodes of a sense amplifier. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification