Dummy block replacement for logic simulation
First Claim
1. A method of reducing a size of a netlist for a hardware target architecture for simulation, comprising:
- create a netlist of objects specifying each object for the target hardware architecture, wherein the target hardware architecture is a field programmable gate array;
identify objects specific to the target hardware architecture that are repeated to identify potential dummy objects;
create a list of objects, from the netlist of objects, that are used by a circuit design to be implemented in the target hardware architecture;
form a list of unused objects in the target hardware architecture from the netlist of objects and the list of objects used by the circuit design;
replace at least one object in the netlist of objects for the target hardware architecture that is also specified in the list of unused objects and which is identified as a potential dummy object with an appropriate dummy object to form a modified netlist by removing functional hardware description language from the object; and
simulate the modified netlist by simulating each object of the modified netlist inclusive of each dummy object, wherein for each dummy object, a signal provided to the dummy object is fed through the dummy object unchanged.
1 Assignment
0 Petitions
Accused Products
Abstract
A method (10) of reducing a size of a netlist for a target architecture can include the steps of creating (12) a netlist of objects for the target architecture, identifying (14) objects specific to the target architecture that are repeated regularly to identify potential dummy objects, creating (15) a list of objects used by a design in the target architecture, and forming (16) a list of unused objects in the target architecture from the netlist of objects and the list of objects used by the design. The method can further include the steps of replacing (18) at least one object in the list of unused objects with an appropriate dummy object to form a modified netlist and simulating (19) the modified netlist.
34 Citations
17 Claims
-
1. A method of reducing a size of a netlist for a hardware target architecture for simulation, comprising:
-
create a netlist of objects specifying each object for the target hardware architecture, wherein the target hardware architecture is a field programmable gate array; identify objects specific to the target hardware architecture that are repeated to identify potential dummy objects; create a list of objects, from the netlist of objects, that are used by a circuit design to be implemented in the target hardware architecture; form a list of unused objects in the target hardware architecture from the netlist of objects and the list of objects used by the circuit design; replace at least one object in the netlist of objects for the target hardware architecture that is also specified in the list of unused objects and which is identified as a potential dummy object with an appropriate dummy object to form a modified netlist by removing functional hardware description language from the object; and simulate the modified netlist by simulating each object of the modified netlist inclusive of each dummy object, wherein for each dummy object, a signal provided to the dummy object is fed through the dummy object unchanged. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method of processing signals with a modified netlist within a software-based logic simulation tool comprising the step of:
-
creating a netlist of objects specifying each object for a target hardware architecture, wherein the target hardware architecture is a field programmable gate array; identifying objects specific to the target hardware architecture that are repeated to identify potential dummy object; creating a list objects, from the netlist of objects, that are used by a circuit design to be implemented in the target hardware architecture; forming a list of unused objects in the target hardware architecture from the netlist of objects and the list of objects used by the circuit design; replacing any at least one object in the netlist of objects for the target hardware architecture that is also specified in the list of unused object and which is identified as a potential dummy object with an appropriate dummy object to form a modified netlist by removing functional hardware description language from the object; and simulating the modified netlist by simulating each object of the modified netlist inclusive of each dummy object, wherein for each dummy object, a signal provided to the dummy object is fed through the dummy object unchanged. - View Dependent Claims (12)
-
-
13. A machine readable storage, having stored thereon a computer program having a plurality of code sections executable by a machine for causing the machine to perform the steps of:
-
create a netlist of objects specifying each object for a target hardware architecture, wherein the target hardware architecture is a field programmable gate array; identify objects specific to the target hardware architecture that are repeated to identify potential dummy objects; create a list of objects used by a circuit design to be implemented in the target hardware architecture; form a list of unused objects in the target hardware architecture from the netlist of objects and the list of objects used by the circuit design; replace at least one object in the netlist of the target hardware architecture that is also specified in the list of unused objects and which is identified as a potential dummy object with an appropriate dummy object to form a modified netlist by removing functional hardware description language from the object; and simulate the modified netlist by simulating each object of the modified netlist inclusive of each dummy object, wherein for each dummy object, a signal provided to the dummy object is fed through the dummy object unchanged. - View Dependent Claims (14)
-
-
15. A system for simulating a circuit design for target hardware architectures for implementation on field programmable gate arrays comprising:
-
means for creating a netlist of objects specifying each object for the target hardware architecture, wherein the target hardware architecture is a field programmable gate array; means for identifying objects specific to the target hardware architecture that are repeated to identify potential dummy objects; means for creating a list of objects used by the circuit design in the target hardware architecture; means for forming a list of unused objects in the target hardware architecture from the netlist of objects and the list of objects used by the circuit design; means for replacing at least one object in the netlist of the target hardware architecture that is also specified in the list of unused objects and which is identified as a potential dummy object with an appropriate dummy object to form a modified netlist by removing functional hardware description language from the object; and means for simulating the modified netlist by simulating each object of the modified netlist inclusive of each dummy object, wherein for each dummy object, a signal provided to the dummy object is fed through the dummy object unchanged. - View Dependent Claims (16, 17)
-
Specification