Apparatus and method for pipelined memory operations

• US 7,330,951 B2
• Filed: 11/08/2005
• Issued: 02/12/2008
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Tsern, Ely K., Hampel, Craig E., Stark, Donald C., Ware, Frederick A., Horowitz, Mark A.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US11/270,251
• Publication Number:
  US 20060059299A1
• Time in Patent Office: 826 Days
• Field of Search: 711/167,168,169,105,103,104 713/400,401,500,501 365/233,189,189.08,221,189.03
• US Class Current: 711/167
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

Claims

1. A semiconductor memory device comprising:

a memory core including eight banks of dynamic random access storage cells;

an internal data bus coupled to the memory core, the internal data bus to transfer M bits of data with a selected bank of the eight banks;

a first interface to transfer N bits of the data, during a single transfer cycle, with first connections external to the semiconductor memory device, wherein M is at least eight times N; and

a second interface to receive encoded control information and a plurality of mask bits from second connections external to the semiconductor memory device, wherein each mask bit of the plurality of mask bits indicates whether to write a corresponding portion of the data to the memory core in the event that the encoded control information specifies a write transaction.

2. A semiconductor memory device comprising:

a memory core including at least eight banks of dynamic random access storage cells wherein the at least eight banks of storage cells are independent in that, while in operation, a sense operation is performed in a first bank of the at least eight banks while a precharge operation is performed in a second bank of the at least eight banks;

a clock signal interface to receive an external clock signal that includes first and second phases;

a first interface to receive a write command;

a second interface to receive data corresponding to the write command during the first and second phases of the external clock signal; and

a third interface to receive a plurality of mask bits, wherein, each mask bit of the plurality of mask bits indicates whether to write corresponding sets of data bits of the data to the memory core.

3. The semiconductor memory device of claim 2, wherein the first interface receives a first sixteen bits of the data during the first phase of the external clock signal and a second sixteen bits of the data during the second phase of the external clock signal, and wherein the plurality of mask bits includes:

a first mask bit that indicates whether to write a first byte of the first sixteen bits of the data to the memory core;

a second mask bit that indicates whether to write a second byte of the first sixteen bits of the data to the memory core;

a third mask bit that indicates whether to write a first byte of the second sixteen bits of the data to the memory core; and

a fourth mask bit that indicates whether to write a second byte of the second sixteen bits of the data to the memory core.

4. The semiconductor memory device of claim 3, wherein the first phase of the external clock signal includes a first edge transition of the external clock signal and the second phase of the external clock signal includes a second edge transition of the external clock signal, wherein the second edge transition is an opposite edge transition with respect to the first edge transition, and wherein:

the third interface receives the first mask bit and the second mask bit during the first phase of the external clock signal; and

the third interface receives the third mask bit and the fourth mask bit during the second phase of the external clock signal.

5. A semiconductor memory device comprising:

a memory core including eight banks of dynamic random access storage cells;

an internal data bus coupled to the memory core, the internal data bus to transfer M bits of data;

a first interface coupled to first connections external to the semiconductor memory device to transfer N bits of the data, during a single transfer cycle, wherein M is at least eight times N, and wherein;

during a read transaction, the data is transferred from a selected bank of the eight banks to the first connections external to the semiconductor memory device; and

during a write transaction, the data is transferred from the first connections external to the semiconductor memory device to a selected bank of the eight banks;

a second interface to receive encoded control information from second connections external to the semiconductor memory device; and

a third interface to receive a plurality of mask bits from third connections external to the memory device, wherein each mask bit of the plurality of mask bits indicates whether to write a corresponding portion of the data to the memory core in the event that the encoded control information specifies a write transaction.

6. The semiconductor memory device of claim 5, further including a clock signal interface to receive an external clock signal that includes a first phase and a second phase, and wherein the data is transferred between the second interface and the second connections on both the first and second phases of the external clock signal.

7. The semiconductor memory device of claim 5, further including a clock signal interface to receive an external clock signal and generate an internal clock signal to time the transfer of the data such that the data is transferred in a controlled phase relationship with the external clock signal.

8. The semiconductor memory device of claim 7, wherein the circuit to receive the external clock signal includes one of a delay locked circuitry and phase locked circuitry.

9. A semiconductor memory device comprising:

a memory core having a plurality of dynamic random access storage cells;

a first interface to receive a write command that specifies a write operation;

a second interface to receive a first set of data bits and a second set of data bits;

a clock signal interface to receive an external clock signal, wherein;

the first set of data bits is received during a first phase of the external clock signal wherein the first phase of the external clock signal includes a first edge transition; and

the second set of the data bits is transferred on a second phase of the external clock signal, wherein the second phase of the external clock signal includes a second edge transition, wherein the second edge transition is an opposite edge transition with respect to the first edge transition;

a third interface to receive a plurality of mask bits, wherein the plurality of mask bits indicates whether to write the first set of data bits to the memory core during the write operation and whether to write the second set of data bits to the memory core during the write operation; and

an internal data bus coupled to the memory core, the internal data bus to provide the first set of data bits and the second set of data bits to be written to the memory core during the write operation, wherein both the first set of data bits and the second set of data bits are each one eighth the total number of bits transferred to the memory core during the write operation.

10. The semiconductor memory device of claim 9, further comprising:

a plurality of banks, wherein the write operation is performed in a first bank of the plurality of banks.

11. The semiconductor memory device of claim 10, wherein a sense operation is performed in a second bank of the plurality of banks while a precharge operation is performed in a third bank of the plurality of banks.

12. The semiconductor memory device of claim 9, wherein the first set of data bits is a first sixteen bits and the second set of data bits is a second sixteen bits, and wherein the plurality of mask bits includes:

a first mask bit that indicates whether to write a first byte of the first sixteen bits to the memory core during the write operation;

a second mask bit that indicates whether to write a second byte of the first sixteen bits of the data to the memory core during the write operation;

a third mask bit that indicates whether to write a first byte of the second sixteen bits of the data to the memory core during the write operation; and

a fourth mask bit that indicates whether to write a second byte of the second sixteen bits of the data to the memory core during the write operation.

13. The semiconductor memory device of claim 9, further including a circuit to receive the external clock signal and generate an internal clock signal having a controlled phase relationship with the external clock signal, wherein the internal clock signal is used to receive the first set of data bits and the second set of data bits.

14. A method of operating a semiconductor memory device that includes a memory core, the method comprising:

providing a write command to the semiconductor memory device;

providing to the semiconductor memory device, a first sixteen bits of data during a first phase of a clock signal and a second sixteen bits of data during a second phase of the clock signal;

providing, to the semiconductor memory device during the first phase of the clock signal, a first mask bit and a second mask bit, wherein;

the first mask bit indicates whether to write a first byte of the first sixteen bits of data to the memory core; and

the second mask bit indicates whether to write a second byte of the first sixteen bits of data to the memory core; and

providing, to the semiconductor memory device during the second phase of the clock signal, a third mask bit and a fourth mask bit, wherein;

the third mask bit indicates whether to write a first byte of the second sixteen bits of data to the memory core; and

the fourth mask bit indicates whether to write a second byte of the second sixteen bits of data to the memory core.

15. The method of claim 14, further comprising:

before providing the write command, providing a sense command that is directed to a first bank of the semiconductor memory device, wherein the sense command indicates that the semiconductor memory device perform a sense operation; and

performing a precharge operation in a second bank of the semiconductor memory device at the same time as performing the sense operation.

16. The method of claim 14, wherein the first phase of the clock signal includes a first edge transition of the clock signal and the second phase of the external clock signal includes a second edge transition of the clock signal, wherein the second edge transition is an opposite edge transition with respect to the first edge transition.

17. A method of operation in a semiconductor memory device having at least a first bank of storage cells and a second bank of storage cells, the method comprising:

receiving an external clock signal that includes a rising edge transition and a falling edge transition;

performing a sense operation in the first bank of storage cells;

while performing the sense operation, performing a precharge operation in the second bank of storage cells;

receiving a write command from a first set of external connections;

receiving a plurality of data bits that correspond to the write command from a second set of external connections;

receiving a plurality of mask bits from a third set of external connections, during both the rising edge transition and the falling edge transition of the external clock signal, wherein each mask bit of the plurality of mask bits indicates whether to write a corresponding portion of the plurality of data bits to the memory core; and

after performing the sense operation in the first bank, transferring the plurality of data bits to the first bank in response to the write command and in accordance with the plurality of mask bits.

18. The method of claim 17, further comprising:

receiving a row address corresponding to a row in the first bank for the sense operation; and

receiving a column address corresponding to a column location in the first bank for the write command.

19. A method of operation in a semiconductor memory device having a memory core including a plurality of dynamic random access storage cells, the method comprising;

receiving an external clock signal that includes a rising edge transition and a falling edge transition;

transferring M bits of data between an internal data bus and the memory core;

transferring between a first set of external connections and a data transport unit, N bits of the data, wherein M is at least eight times N, wherein the data is transferred on both the rising edge transition and the falling edge transition of the external clock signal;

receiving encoded control information from a second set of external connections; and

receiving a plurality of mask bits from a third set of external connections, wherein each mask bit of the plurality of mask bits indicates whether to write a byte of the data to the memory core in the event that the encoded control information specifies a write transaction.

20. The method of claim 19, further comprising performing a sense operation in a first bank of the memory core;

after performing the sense operation, accessing the M bits of data from the first bank of the memory core; and

while performing the sense operation, performing a precharge operation in a second bank of the memory core.

21. The method of claim 19, further comprising:

receiving a read command from the second set of external connections;

transporting from the memory core, a first plurality of data bits along the internal data bus; and

transferring a subset of the first plurality of data bits from the internal data bus to the first set of external connections in response to the read command, such that the subset of the first plurality of data bits is output on the first set of external connections on a single phase of the external clock signal, wherein the first plurality of data bits is eight times the subset of the first plurality of data bits.

22. A method of operation in a semiconductor memory device having a memory core including at least eight banks of dynamic random access storage cells, the method comprising;

receiving an external clock signal that includes a first phase and a second phase;

performing a sense operation in a first bank of the at least eight banks;

while performing the sense operation, performing a precharge operation in a second bank of the at least eight banks;

receiving a write command from a first set of external connections;

receiving a plurality of data bits that corresponds to the write command from a second set of external connections;

receiving a plurality of mask bits from a third set of external connections, wherein each mask bit of the plurality of mask bits indicates whether to write a portion of the plurality of data bits to the memory core in response to the write command wherein receiving the plurality of mask bits includes;

receiving a first mask bit of the plurality of mask bits during the first phase of the external clock signal; and

receiving a second mask bit of the plurality of mask bits during the second phase of the external clock signal; and

after performing the sense operation in the first bank, transferring the plurality of data bits to the first bank in accordance with the plurality of mask bits and in response to the write command.