Integrated circuit memory device having delayed write timing based on read response time

• US 7,330,952 B2
• Filed: 03/27/2007
• Issued: 02/12/2008
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Nguyen, David, Hampel, Craig E., Stark, Donald C., Ware, Frederick A., Davis, Paul G., Abhyankar, Abhijit M., Gasbarro, James A.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US11/692,159
• Publication Number:
  US 20070242532A1
• Time in Patent Office: 322 Days
• Field of Search: 711/167, 711/169, 711/168, 711/105, 711/5, 711/100, 711/154, 365/289, 365/190, 365/222, 365/233, 365/230.03, 365/189.01, 370/375
• US Class Current: 711/167
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2218 Late write
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.

Claims

1. An integrated circuit memory device comprising:

a memory core including a plurality of memory cells;

a pin to receive a clock signal;

a first set of pins to receive, using the clock signal;

a write command to specify that the memory device receive write data and store the write data in the memory core; and

a read command to specify that the memory device output read data accessed from the memory core, wherein the first set of pins receive the read command after the first set of pins receive the write command; and

a second set of pins to receive the write data after a first delay time has transpired from when the write command is received at the first set of pins;

the second set of pins to provide, for each pin of the second set of pins, output of at least two bits of the read data after a second delay time transpires from when the read command is received, wherein the at least two bits of the read data are provided during a clock cycle of the clock signal, wherein the second delay time is based on the first delay time.

2. The integrated circuit memory device of claim 1, wherein the second delay time is based on the first delay time such that the second delay time matches the first delay time minus a channel turnaround time.

3. The integrated circuit memory device of claim 1, further including a circuit to assert, in response to the write command and after a third delay time transpires from when the write command is received at the first set of pins, control information to store the write data in the memory core.

4. The integrated circuit memory device of claim 1, further including a third set of pins that receive a ground potential voltage, wherein the third set of pins are non-connected with respect to bond pads that are included on the integrated circuit memory device.

5. An integrated circuit memory device comprising:

a memory core including a plurality of memory cells;

a pin to receive a clock signal;

a first set of pins to receive, using the clock signal;

a write command to specify that the memory device receive write data and store the write data in the memory core during a write operation, wherein control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device; and

a read command to specify that the memory device output read data accessed from the memory core, wherein the first set of pins receive the read command after the first set of pins receive the write command; and

a second set of pins to output the read data after a first delay time transpires from when the read command is received, wherein each pin of the second set of pins outputs two bits of the read data during a clock cycle of the clock signal, the second set of pins to receive the write data after a second delay time has transpired from when the write command is received at the first set of pins, wherein the second delay time is based on the first delay time.

6. The integrated circuit memory device of claim 5, wherein the second delay time is based on the first delay time such that the second delay time matches the first delay time minus a channel turnaround time.

7. The integrated circuit memory device of claim 5, wherein the first set of pins receive an activate command using the clock signal;

and

the integrated circuit memory device further including a third set of pins to receive a row address and a first column address and a second column address, wherein;

the activate command specifies that the memory device sense a row of memory cells of the plurality of memory cells identified by the row address;

the first column address identifies a column location at which to store the write data; and

the second column address identifies a column location to at which obtain the read data.

8. The integrated circuit memory device of claim 7, wherein

the first set of pins receives the activate command during a first command cycle, the write command during a second command cycle, and the read command during a third command cycle;

and

the third set of pins receives the row address during the first command cycle, the first column address during the second command cycle, and the third column address during the third command cycle.

9. The integrated circuit memory device of claim 7, wherein

the activate command is included in a first packet;

the write command is included in a second packet; and

the read command is included in a third packet.

10. The integrated circuit memory device of claim 5, further including a third set of pins that receive a ground potential voltage, wherein the third set of pins are non-connected with respect to bond pads that are included on the integrated circuit memory device.

11. The integrated circuit memory device of claim 5, further comprising a third set of pins to receive an activate command, wherein the activate command specifies that the memory device sense a row of memory cells in the memory core.

12. The integrated circuit memory device of claim 11, wherein

the activate command is included in a first packet;

the write command is included in a second packet; and

the read command is included in a third packet.

13. An integrated circuit memory device comprising:

a memory core including a plurality of memory cells;

a first set of pins to receive a write command, and to receive a read command after the write command, wherein;

the write command specifies that the memory device receive write data, wherein control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating storage of the write data in the memory core; and

the read command specifies that the memory device output read data accessed from the memory core; and

a second set of pins to receive the write data after a write delay time has transpired from when the write command is received at the first set of pins, the second set of pins to provide the read data after a read delay time transpires from when the read command is received at the first set of pins, wherein the write delay time is based on the read delay time.

14. The integrated circuit memory device of claim 13, wherein the write delay time is based on the read delay time such that the write delay time matches the read delay time minus a channel turnaround time.

15. The integrated circuit memory device of claim 13, wherein the first set of pins receive an activate command;

and

wherein the integrated circuit memory device further includes a third set of pins to receive a row address, a first column address, and a second column address, wherein;

the activate command specifies that the memory device sense a row of memory cells of the plurality of memory cells identified by the row address;

the first column address identifies a column location at which to store the write data; and

the second column address identifies a column location to at which obtain the read data.

16. A method of operation of an integrated circuit memory device having a memory core including a plurality of memory cells, the method comprising:

receiving a sense command that specifies that the memory device activate a row of memory cells of the plurality of memory cells included in the memory core;

while receiving the sense command, receiving a row address that identifies the row;

receiving a write command that specifies that the memory device receive write data;

receiving a read command after receiving the write command;

in response to the read command, outputting read data after a read delay time transpires from when the read command is received;

receiving the write data after a first write delay time has transpired from when the write command is received, wherein the first write delay time is based on the read delay time; and

after a second write delay time transpires from when the write command is received, asserting a control signal, in response to the write command, to cause the write data to be stored in the row.

17. The method of claim 16, further comprising:

receiving a column address that identifies a location in the row to store the write data; and

receiving a column address that identifies a location in the row in which to obtain the read data in response to the read command.

18. The method of claim 16, further comprising;

receiving a clock signal; and

wherein receiving the write data includes receiving two consecutive bits of the write data at a pin of the integrated circuit memory device during a clock cycle of the clock signal.

19. The method of claim 16, further comprising;

receiving a clock signal; and

wherein outputting the read data includes outputting two consecutive bits of the read data at a pin of the integrated circuit memory device during a clock cycle of the clock signal.

20. The method of claim 16, wherein the third delay time is based on the second delay time such that the third delay time matches the second delay time minus a channel turnaround time.

21. A method of operating an integrated circuit memory device that receives clock signals and includes a memory core having a plurality of banks, the method comprising:

providing a sense command to the memory device, wherein the sense command specifies that the memory device activate a row of memory cells in a bank identified by a first bank address;

providing a row address to the memory device, wherein the row address identifies the row of memory cells in the bank identified by the first bank address;

providing a read command to the memory device after providing the sense command, wherein the read command initiates a read operation such that data is output from the memory device after a first delay time transpires;

providing a write command to the memory device after providing the sense command, wherein the write command specifies that the memory device receive write data and store the write data in a row of memory cells in a bank identified by a second bank address, wherein the write command is presented internally within the memory device after a second delay time has transpired from when the write command is received;

providing a column address to the memory device, wherein the column address identifies a location within the row of memory cells in the bank identified by the second bank address; and

providing the write data to the memory device after a third delay time has transpired after providing the write command, wherein the third delay time is based on the first delay time.

22. The method of claim 21, wherein providing the write data includes providing two consecutive bits of the write data to a pin of the integrated circuit memory device during a clock cycle of a clock signal.

23. The method of claim 21, wherein the third delay time is based on the first delay such that the third delay time matches the first delay time minus a channel turnaround time.

24. The method of claim 21, wherein the first bank address and the second bank address identify the same bank of the plurality of banks.

25. The method of claim 21, wherein the sense command is included in a first control packet and the write command is included in a second control packet.

26. A method of operation of an integrated circuit memory device that includes a memory core having a plurality of memory cells;

receiving, using a clock signal, a row address at a first set of pins,

after receiving the row address, receiving, a column address at the first set of pins;

receiving, using the clock signal, a sense command at a second set of pins, wherein the sense command specifies that the memory device activate a row of memory cells of the plurality of memory cells identified by the row address;

receiving, using the clock signal, a write command at the second set of pins, wherein the write command specifies that the memory device receive write data and store the write data at a column of the row of memory cells, the column identified by the column address;

presenting the write command internally after a first delay time has transpired from when the write command was received;

receiving a read command at the second set of pins, wherein the read command specifies a read operation to the memory device;

outputting read data from a third set of pins of the memory device after a second delay time transpires from receiving read command;

receiving the write data at the third set of pins, after a third delay time has transpired from when the write command was received, wherein the third delay time is based on the second delay time.

27. The method of claim 26, wherein receiving the write data includes receiving two consecutive bits of the write data at a pin of the third set of pins during a first clock cycle of the clock signal, and wherein outputting the read data includes outputting two consecutive bits of the read data at the pin during a second clock cycle of the clock signal.

28. The method of claim 26, wherein the third delay time is based on the second delay time such that the third delay time matches the second delay time minus a channel turnaround time.