System and method for read synchronization of memory modules
First Claim
1. A memory module, comprising:
- a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests;
a read synchronization module coupled to the memory device interface, the read synchronization module operable to compare timing between coupling read data from the memory devices and coupling read data from the memory hub and to generate an adjust signal corresponding to the compared timing; and
a memory sequencer coupled to the link interface, the memory device interface, and the read synchronization module, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to adjust the timing at which read memory requests are coupled to the memory device interface responsive to the adjust signal.
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Accused Products
Abstract
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.
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Citations
36 Claims
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1. A memory module, comprising:
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a plurality of memory devices; and a memory hub, comprising; a link interface receiving memory requests for access to at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests; a read synchronization module coupled to the memory device interface, the read synchronization module operable to compare timing between coupling read data from the memory devices and coupling read data from the memory hub and to generate an adjust signal corresponding to the compared timing; and a memory sequencer coupled to the link interface, the memory device interface, and the read synchronization module, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to adjust the timing at which read memory requests are coupled to the memory device interface responsive to the adjust signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory module, comprising:
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a plurality of memory devices, each of the memory devices being operable to output read data signals and a read data strobe signal responsive to respective memory requests; and a memory hub, comprising; a link interface receiving memory requests for access to at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to couple the received memory requests to at least one of the memory devices and to receive the read data signals and the read data strobe signal responsive to respective memory requests; a buffer coupled to receive the read data signals, the read data signals being clocked into the buffer responsive to the read data strobe signal; a read synchronization module coupled to the memory device interface, the read synchronization module operable to compare timing between the read data strobe signals and a core clock signal and to generate an adjust signal corresponding to the compared timing; and a memory sequencer coupled to the link interface, the memory device interface, and the read synchronization module, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to adjust the timing at which read memory requests are coupled to the memory device interface responsive to the adjust signal. - View Dependent Claims (9, 10, 11, 12)
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13. A memory hub, comprising:
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a link interface receiving memory requests for access to memory cells in at least one memory device; a memory device interface coupled to a plurality of memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests; a read synchronization module coupled to the memory device interface, the read synchronization module operable to compare timing between coupling read data from the memory devices and coupling read data from the memory hub and to generate an adjust signal corresponding to the compared timing; and a memory sequencer coupled to the link interface, the memory device interface, and the read synchronization module, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to adjust the timing at which read memory requests are coupled to the memory device interface responsive to the adjust signal. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A computer system, comprising:
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a central processing unit (“
CPU”
);a system controller coupled to the CPU, the system controller having an input port and an output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising; a plurality of memory devices; and a memory hub, comprising; a link interface receiving memory requests for access to at least one of the memory devices; a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to at least one of the memory devices and to receive read data responsive to at least some of the memory requests; a read synchronization module coupled to the memory device interface, the read synchronization module operable to compare timing between coupling read data from the memory devices and coupling read data from the memory hub and to generate an adjust signal corresponding to the compared timing; and a memory sequencer coupled to the link interface, the memory device interface, and the read synchronization module, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to adjust the timing at which read memory requests are coupled to the memory device interface responsive to the adjust signal. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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27. A method of reading data from a memory module, comprising:
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receiving memory requests for access to a memory device in the memory module; coupling the memory requests to the memory device responsive to the received memory request, at least some of the memory requests being memory requests to read data; receiving read data responsive to the read memory requests; outputting the read data from the memory module; comparing timing between receiving the read data and outputting the read from the memory module; and adjusting the timing at which read memory requests are coupled to the memory device interface as a function of the compared timing. - View Dependent Claims (28, 29, 30, 31, 32)
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33. A method of coupling read data from a memory device to a buffer and outputting read data from the buffer, comprising:
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coupling memory requests to the memory device, at least some of the memory requests being memory requests to read data; receiving read data responsive to the read memory requests; storing the received read data in the buffer; outputting the read data from the buffer; comparing timing between storing the read data in the buffer and outputting the read from the buffer; and adjusting the timing at which read memory requests are coupled to the memory device interface as a function of the compared timing. - View Dependent Claims (34, 35, 36)
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Specification