Method and system for enhancing circuit design process
First Claim
Patent Images
1. A system for designing an integrated circuit, comprising:
- a) a wire model objects generator (“
WMG”
) for generating and inserting wire model objects (“
WMOs”
) into a schematic of said integrated circuit based on sizing and placement of components of said intergrated circuit;
b) an early timing analyzer for performing an early timing analysis (“
ETA”
) on said schematic; and
c) a central processor for causing said WMG to generate and insert said WMOs, and for generating and inserting new WMOs after re-sizing and/or re-placing said components, if said ETA fails, wherein the WMG comprises;
a connectivity and placement data extractor for retrieving from a first schematic file connectivity and placement data;
a geometry estimator (“
GE”
) for utilizing the retrieved connectivity and placement data to estimate a corresponding wire routing geometry for each signal in the integrated circuit, said wire routing geometry consists of one or more source and target points interconnected by line segments;
a wire model embedder (“
WME”
) for deciding a number and type of WMOs each segment and “
via”
connection will be substituted with; and
an insertion means for generating a second schematic file by inserting the WMOs into the schematic of said integrated circuit, said insertion means determines where to add intermediate nodes to the second schematic file to accommodate for cascading WMOs.
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Abstract
A method is provided for designing an integrated circuit. The method includes inserting wire model objects into the schematic of said circuit based on sizing and placement of components of the circuit, and performing an early timing analysis on said schematic. The steps of inserting and performing are repeated after re-sizing and/or re-placing the components if early timing analysis fails.
34 Citations
2 Claims
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1. A system for designing an integrated circuit, comprising:
-
a) a wire model objects generator (“
WMG”
) for generating and inserting wire model objects (“
WMOs”
) into a schematic of said integrated circuit based on sizing and placement of components of said intergrated circuit;b) an early timing analyzer for performing an early timing analysis (“
ETA”
) on said schematic; andc) a central processor for causing said WMG to generate and insert said WMOs, and for generating and inserting new WMOs after re-sizing and/or re-placing said components, if said ETA fails, wherein the WMG comprises; a connectivity and placement data extractor for retrieving from a first schematic file connectivity and placement data; a geometry estimator (“
GE”
) for utilizing the retrieved connectivity and placement data to estimate a corresponding wire routing geometry for each signal in the integrated circuit, said wire routing geometry consists of one or more source and target points interconnected by line segments;a wire model embedder (“
WME”
) for deciding a number and type of WMOs each segment and “
via”
connection will be substituted with; andan insertion means for generating a second schematic file by inserting the WMOs into the schematic of said integrated circuit, said insertion means determines where to add intermediate nodes to the second schematic file to accommodate for cascading WMOs. - View Dependent Claims (2)
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Specification
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Current AssigneeGoogle LLC (Alphabet Inc.)
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Original AssigneeInternational Business Machines Corporation
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InventorsHeymann, Omer, Leibowitz, Moshe, Noy, Gil, Goren, Lidor, Amit, Niv, Speiser, Maya, Bustin, Ronit, Raphayevich, Alex
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Primary Examiner(s)Lin; Sun James
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Application NumberUS11/232,746Publication NumberTime in Patent Office873 DaysField of Search716/11, 716/12, 716/5, 716/6, 716/9, 716/10US Class Current716/113CPC Class CodesG06F 2119/12 Timing analysis or timing o...G06F 30/327 Logic synthesis; Behaviour ...G06F 30/39 Circuit design at the physi...
