Thin film transistor and manufacturing method thereof

• US 7,332,382 B2
• Filed: 06/30/2005
• Issued: 02/19/2008
• Est. Priority Date: 09/24/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Han, Chang Wook
• Primary Examiner(s): Vu; David
• Application Number:
  US11/172,070
• Publication Number:
  US 20060079042A1
• Time in Patent Office: 964 Days
• Field of Search: 438/197, 438/479, 438/482, 438/486, 438/488, 438/30, 438/149, 438/151, 438/158, 438/159, 257/315, 257/335, 257/369, 257/57, 257/59, 257/66, 257/72, 257/E21.414, 257/E29.151, 257/E29.117
• US Class Current: 438/149
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A method for manufacturing a thin film transistor is provided. In the method, a gate electrode is formed on a substrate. A crystalline gate insulating layer is formed on an entire surface of the substrate having the gate electrode formed thereon. A microcrystalline silicon layer and a doped amorphous silicon layer are sequentially formed on the crystalline gate insulating layer. A metal layer is deposited on the substrate including the crystalline gate insulating layer, the microcrystalline silicon layer and the doped amorphous silicon layer. Source and drain electrodes, an ohmic contact layer and an active layer are formed by etching predetermined portions of the metal layer and the doped amorphous silicon layer to expose a predetermined portion of the microcrystalline silicon layer.

Claims

1. A method for manufacturing a thin film transistor, the method comprising:

forming a gate electrode on a substrate;

forming an amorphous gate insulating layer on the substrate on which the gate electrode is formed;

forming a crystalline gate insulating layer on a surface of the amorphous gate insulating layer;

sequentially forming a microcrystalline silicon layer and a doped silicon layer on the crystalline gate insulating layer;

depositing a metal layer on the substrate including the crystalline gate insulating layer, the silicon layer, and the doped silicon layer; and

exposing a predetermined portion of the silicon layer to form a source electrode, a drain electrode, an ohmic contact layer and an active layer.

2. The method according to claim 1, wherein the crystalline gate insulating layer is formed of a crystalline dielectric material.

3. The method according to claim 2, wherein the crystalline dielectric material comprises ZrO 2 or TiO 2.

4. The method according to claim 1, wherein the crystalline gate insulating layer is deposited at a low temperature through atomic layer deposition (ALD).

5. The method according to claim 1, wherein exposing a predetermined portion of the silicon layer comprises etching.

6. The method according to claim 1, wherein the doped silicon layer comprises doped amorphous silicon.

7. The method according to claim 1, further comprising:

depositing a passivation layer to cover the source electrode and the drain electrode and forming a contact hole for exposing the drain electrode by patterning the deposited passivation layer; and

forming a pixel electrode electrically connected to the drain electrode by depositing a transparent conductive material on the passivation layer.

8. The method according to claim 7, wherein the transparent conductive material is indium-tin oxide (ITO).