Substrate processing method and fabrication process of a semiconductor device

• US 7,332,426 B2
• Filed: 06/02/2005
• Issued: 02/19/2008
• Est. Priority Date: 06/02/2004
• Status: Active Grant

• Current Assignee: Tokyo Electron Limited
• Original Assignee: Tokyo Electron Limited
• Inventors: Ishizaka, Tadahiro, Ikeda, Taro, Hara, Masamichi
• Primary Examiner(s): Smith; Zandra V.
• Assistant Examiner(s): Tran; Thanh Y.
• Application Number:
  US11/142,457
• Publication Number:
  US 20050272247A1
• Time in Patent Office: 992 Days
• Field of Search: 257/758, 257/774, 257/751, 257/773, 257/E21.212, 438/475, 438/618, 438/620, 438/622, 438/627, 438/629, 438/637, 438/639, 438/643, 438/653, 438/672, 438/675, 438/669, 438/FOR.448
• US Class Current: 438/618
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric

Abstract

A method of fabricating a semiconductor device includes the steps of forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath the interlayer insulation film is exposed at a bottom of the via-hole, forming a conductive barrier film on the interlayer insulation film so as to cover a sidewall surface of the via-hole and the exposed metal interconnection pattern in conformity with a shape of the via-hole. and forming a metal film on the conductive barrier film, wherein there is provided a preprocessing step, after the step of forming the via-hole but before the step of forming the conductive barrier film, of processing the interlayer insulation film including the sidewall surface of the via-hole and a bottom surface of the via-hole, with plasma containing hydrogen having energy not causing sputtering of the metal interconnection pattern.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath said interlayer insulation film is exposed at a bottom of said via-hole;

forming a conductive barrier film on said interlayer insulation film so as to cover a sidewall surface of said via-hole and said exposed metal interconnection pattern in conformity with a shape of said via-hole; and

forming a metal film on said conductive barrier film,

wherein there is provided a preprocessing step, after said forming said via-hole but before said forming said conductive barrier film, processing said interlayer insulation film including said sidewall surface of said via-hole and a bottom surface of said via-hole, with plasma containing hydrogen having energy not causing sputtering of said metal interconnection pattern, such that a surface of said interlayer insulation film, said sidewall surface of said via-hole and said bottom surface of said via-hole are terminated by hydrogen,

wherein said forming said conductive barrier film comprises covering said surface of said interlayer insulation film with a conductive nitride film including said sidewall surface and bottom surface of said via-hole, and covering said conductive nitride film by a refractory metal film, and

wherein said forming said conductive nitride film comprises;

a first step covering said surface of said interlayer insulation film and said sidewall surface and bottom surface of said via-hole by organic metal source molecules containing nitrogen, and a second step decomposing said organic metal source molecules, said first step and said second step being repeated with intervening purging steps.

2. The method as claimed in claim 1, wherein said electron temperature of plasma in said preprocessing step does not exceed 3 eV.

3. The method as claimed in claim 1, wherein said plasma of said preprocessing step is excited by a microwave.

4. The method as claimed in claim 1, wherein said plasma of said preprocessing step is excited by emitting a microwave from a planar antenna.

5. The method as claimed in claim 1, wherein said plasma of said preprocessing step is excited by an RF power supplied to an induction coil.

6. The method as claimed in claim 1, wherein said plasma of said preprocessing step is formed by a remote plasma source.

7. The method as claimed in claim 1, wherein said plasma in said preprocessing step is a mixed gas plasma of a rare gas and a reducing gas containing hydrogen.

8. The method as claimed in claim 1, wherein said forming said refractory metal film comprises a third step covering a surface of said conductive nitride film with metal source molecules containing a refractory metal element constituting said refractory metal film and a fourth step decomposing said metal source molecules, said third step and said fourth step being repeated with intervening purging steps.

9. The method as claimed in claim 1, wherein said interlayer insulation film is an SiOCH film formed by a plasma CVD process.

10. The method as claimed in claim 1, wherein said interlayer insulation film is an inorganic SOD film.

11. The method as claimed in claim 1, wherein said interlayer insulation film comprises an organic polymer film.

12. The method as claimed in claim 1, wherein said interlayer insulation film is a porous film.

13. The method as claimed in claim 1, wherein said forming said conductive barrier film is carried out in a first processing vessel, and wherein said forming said metal film is conducted in a second processing vessel connected to said first processing vessel via a vacuum substrate transportation chamber.

14. The method as claimed in claim 1, wherein said preprocessing is carried out in a first processing vessel and said forming said conductive barrier film is carried out in a second processing vessel coupled to said first processing vessel via a first vacuum substrate transportation chamber, said step forming said metal film is carried out in a third processing vessel coupled to a second vacuum substrate transportation chamber, said second vacuum substrate transportation chamber being coupled to said first vacuum substrate transportation chamber via a gate valve.

15. A processor-readable medium storing program code means for configuring a general purpose computer to control a substrate processing system such that said substrate processing apparatus carries out a method of fabricating a semiconductor device, comprising:

forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath said interlayer insulation film is exposed at a bottom of said via-hole;

forming a conductive barrier film on said interlayer insulation film so as to cover a sidewall surface of said via-hole and said exposed metal interconnection pattern in conformity with a shape of said via-hole; and

forming a metal film on said conductive barrier film,

wherein there is provided a preprocessing step, after said forming said via-hole but before said forming said conductive barrier film, processing said interlayer insulation film including said sidewall surface of said via-hole and a bottom surface of said via-hole, with plasma containing hydrogen having energy not causing sputtering of said metal interconnection pattern, such that a surface of said interlayer insulation film, said sidewall surface of said via-hole and said bottom surface of said via-hole are terminated by hydrogen,

wherein said forming said conductive barrier film comprises covering said surface of said interlayer insulation film with a conductive nitride film including said sidewall surface and bottom surface of said via-hole, and covering said conductive nitride film by a refractory metal film, and

wherein said forming said conductive nitride film comprises;

a first step covering said surface of said interlayer insulation film and said sidewall surface and bottom surface of said via-hole by organic metal source molecules containing nitrogen, and a second step decomposing said organic metal source molecules, said first step and said second step being repeated with intervening purging steps.

16. The processor-readable medium as claimed in claim 15, wherein said electron temperature of plasma in said preprocessing step does not exceed 3 eV.

17. The processor-readable medium as claimed in claim 15, wherein said plasma in said preprocessing step is a mixed gas plasma of a rare gas and a reducing gas containing hydrogen.

18. The processor-readable medium as claimed in claim 15, wherein said step covering said conductive nitride film by a refractory metal film comprises a third step covering a surface of said conductive nitride film with metal source molecules containing a refractory metal element constituting said refractory metal film and a fourth step decomposing said metal source molecules, said third step and said fourth step being repeated with intervening purging steps.

19. The processor-readable medium as claimed in claim 15, wherein said forming said conductive barrier film is carried out in a first processing vessel, and wherein said forming said metal film is conducted in a second processing vessel connected to said first processing vessel via a vacuum substrate transportation chamber.

20. The processor-readable medium as claimed in claim 15, wherein said preprocessing is carried out in a first processing vessel and said forming said conductive barrier film is carried out in a second processing vessel coupled to said first processing vessel via a first vacuum substrate transportation chamber, said forming said metal film is carried out in a third processing vessel coupled to a second vacuum substrate transportation chamber, said second vacuum substrate transportation chamber being coupled to said first vacuum substrate transportation chamber via a gate valve.

21. A method of fabricating a semiconductor device, comprising:

forming a via-hole in an interlayer insulation film such that a metal interconnection pattern formed underneath said interlayer insulation film is exposed at a bottom of said via-hole;

forming a conductive barrier film on said interlayer insulation film so as to cover a sidewall surface of said via-hole and said exposed metal interconnection pattern in conformity with a shape of said via-hole; and

forming a metal film on said conductive barrier film,

wherein there is provided a preprocessing step, after said forming said via-hole but before said forming said conductive barrier film, processing said interlayer insulation film including said sidewall surface of said via-hole and a bottom surface of said via-hole, with plasma containing hydrogen having energy not causing sputtering of said metal interconnection pattern, such that a surface of said interlayer insulation film, said sidewall surface of said via-hole and said bottom surface of said via-hole are terminated by hydrogen, and

wherein said forming said conductive barrier film comprises covering said surface of said interlayer insulation film with a conductive nitride film including said sidewall surface and bottom surface of said via-hole, and covering said conductive nitride film by a refractory metal film,

said forming said refractory metal film comprises a third step covering a surface of said conductive nitride film with metal source molecules containing a refractory metal element constituting said refractory metal film and a fourth step decomposing said metal source molecules, said third step and said fourth step being repeated with intervening purging steps.

22. The method as claimed in claim 21, wherein said interlayer insulation film is an SiOCH film formed by a plasma CVD process.

23. The method as claimed in claim 21, wherein said interlayer insulation film is an inorganic SOD film.

24. The method as claimed in claim 21, wherein said interlayer insulation film comprises an organic polymer film.

25. The method as claimed in claim 21, wherein said interlayer insulation film is a porous film.

26. The method as claimed in claim 21, wherein said step of forming said conductive barrier film is carried out in a first processing vessel, and wherein said step of forming said metal film is conducted in a second processing vessel connected to said first processing vessel via a vacuum substrate transportation chamber.